| microchip_pfsoc.c (a05f8ecd88f15273d033b6f044b850a8af84a5b8) | microchip_pfsoc.c (732612856a8948a6ba1148322651743aa963b51c) |
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| 1/* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * --- 72 unchanged lines hidden (view full) --- 81 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 82 * https://www.microsemi.com/document-portal/doc_download/ 83 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 84 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 85 * describes the complete integrated peripherals memory map 86 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 87 * describes the complete IOSCB modules memory maps 88 */ | 1/* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * --- 72 unchanged lines hidden (view full) --- 81 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 82 * https://www.microsemi.com/document-portal/doc_download/ 83 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 84 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 85 * describes the complete integrated peripherals memory map 86 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 87 * describes the complete IOSCB modules memory maps 88 */ |
| 89static const struct MemmapEntry { 90 hwaddr base; 91 hwaddr size; 92} microchip_pfsoc_memmap[] = { | 89static const MemMapEntry microchip_pfsoc_memmap[] = { |
| 93 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 94 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 95 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 97 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 98 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 99 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 100 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, --- 76 unchanged lines hidden (view full) --- 177 178 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 179} 180 181static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 182{ 183 MachineState *ms = MACHINE(qdev_get_machine()); 184 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); | 90 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 91 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 92 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 97 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, --- 76 unchanged lines hidden (view full) --- 174 175 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 176} 177 178static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 179{ 180 MachineState *ms = MACHINE(qdev_get_machine()); 181 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); |
| 185 const struct MemmapEntry *memmap = microchip_pfsoc_memmap; | 182 const MemMapEntry *memmap = microchip_pfsoc_memmap; |
| 186 MemoryRegion *system_memory = get_system_memory(); 187 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 188 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 189 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 190 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 191 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 192 char *plic_hart_config; 193 size_t plic_hart_config_len; --- 252 unchanged lines hidden (view full) --- 446 type_register_static(µchip_pfsoc_soc_type_info); 447} 448 449type_init(microchip_pfsoc_soc_register_types) 450 451static void microchip_icicle_kit_machine_init(MachineState *machine) 452{ 453 MachineClass *mc = MACHINE_GET_CLASS(machine); | 183 MemoryRegion *system_memory = get_system_memory(); 184 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 185 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 186 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 187 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 188 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 189 char *plic_hart_config; 190 size_t plic_hart_config_len; --- 252 unchanged lines hidden (view full) --- 443 type_register_static(µchip_pfsoc_soc_type_info); 444} 445 446type_init(microchip_pfsoc_soc_register_types) 447 448static void microchip_icicle_kit_machine_init(MachineState *machine) 449{ 450 MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 454 const struct MemmapEntry *memmap = microchip_pfsoc_memmap; | 451 const MemMapEntry *memmap = microchip_pfsoc_memmap; |
| 455 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 456 MemoryRegion *system_memory = get_system_memory(); 457 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 458 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 459 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 460 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 461 uint64_t mem_high_size; 462 DriveInfo *dinfo = drive_get_next(IF_SD); --- 91 unchanged lines hidden --- | 452 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 453 MemoryRegion *system_memory = get_system_memory(); 454 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 455 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 456 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 457 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 458 uint64_t mem_high_size; 459 DriveInfo *dinfo = drive_get_next(IF_SD); --- 91 unchanged lines hidden --- |