boot.c (dc144fe13d336caac2f03b57f1df738e84f984ec) boot.c (8590f53661ec678fd3aa97b4da212b0c00056c2e)
1/*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

--- 212 unchanged lines hidden (view full) ---

221 &address_space_memory);
222}
223
224void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
225 hwaddr rom_size, uint64_t kernel_entry,
226 uint32_t fdt_load_addr, void *fdt)
227{
228 int i;
1/*
2 * QEMU RISC-V Boot Helper
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

--- 212 unchanged lines hidden (view full) ---

221 &address_space_memory);
222}
223
224void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
225 hwaddr rom_size, uint64_t kernel_entry,
226 uint32_t fdt_load_addr, void *fdt)
227{
228 int i;
229 uint32_t start_addr_hi32 = 0x00000000;
229
230
231 #if defined(TARGET_RISCV64)
232 start_addr_hi32 = start_addr >> 32;
233 #endif
230 /* reset vector */
231 uint32_t reset_vec[10] = {
232 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
233 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
234 0xf1402573, /* csrr a0, mhartid */
235#if defined(TARGET_RISCV32)
236 0x0202a583, /* lw a1, 32(t0) */
237 0x0182a283, /* lw t0, 24(t0) */
238#elif defined(TARGET_RISCV64)
239 0x0202b583, /* ld a1, 32(t0) */
240 0x0182b283, /* ld t0, 24(t0) */
241#endif
242 0x00028067, /* jr t0 */
243 start_addr, /* start: .dword */
234 /* reset vector */
235 uint32_t reset_vec[10] = {
236 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
237 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
238 0xf1402573, /* csrr a0, mhartid */
239#if defined(TARGET_RISCV32)
240 0x0202a583, /* lw a1, 32(t0) */
241 0x0182a283, /* lw t0, 24(t0) */
242#elif defined(TARGET_RISCV64)
243 0x0202b583, /* ld a1, 32(t0) */
244 0x0182b283, /* ld t0, 24(t0) */
245#endif
246 0x00028067, /* jr t0 */
247 start_addr, /* start: .dword */
244 0x00000000,
248 start_addr_hi32,
245 fdt_load_addr, /* fdt_laddr: .dword */
246 0x00000000,
247 /* fw_dyn: */
248 };
249
250 /* copy in the reset vector in little_endian byte order */
251 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
252 reset_vec[i] = cpu_to_le32(reset_vec[i]);
253 }
254 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
255 rom_base, &address_space_memory);
256 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
257 kernel_entry);
258
259 return;
260}
249 fdt_load_addr, /* fdt_laddr: .dword */
250 0x00000000,
251 /* fw_dyn: */
252 };
253
254 /* copy in the reset vector in little_endian byte order */
255 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
256 reset_vec[i] = cpu_to_le32(reset_vec[i]);
257 }
258 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
259 rom_base, &address_space_memory);
260 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
261 kernel_entry);
262
263 return;
264}