ppc_booke.c (783eb67e7a125eaf226e5ea4f5df97c1ea42311e) ppc_booke.c (a1f7f97b950a46393b0e55a9a0082e70f540cbbd)
1/*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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29#include "qemu/log.h"
30#include "hw/loader.h"
31#include "kvm_ppc.h"
32
33
34/* Timer Control Register */
35
36#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
1/*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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29#include "qemu/log.h"
30#include "hw/loader.h"
31#include "kvm_ppc.h"
32
33
34/* Timer Control Register */
35
36#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
37#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT)
37#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
38#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
38#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
39#define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT)
40#define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */
41#define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */
39#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
40#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
41#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
42#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
42#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
43#define TCR_FP_MASK (0x3 << TCR_FP_SHIFT)
44#define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
45#define TCR_ARE (1 << 22) /* Auto-Reload Enable */
43#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
44#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
45#define TCR_ARE (1U << 22) /* Auto-Reload Enable */
46
47/* Timer Control Register (e500 specific fields) */
48
49#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
50#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
51#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
52#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
53
54/* Timer Status Register */
55
46
47/* Timer Control Register (e500 specific fields) */
48
49#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
50#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
51#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
52#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
53
54/* Timer Status Register */
55
56#define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */
57#define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */
56#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
57#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
58#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
58#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
59#define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT)
60#define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */
61#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */
59#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
60#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
61#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
62
63typedef struct booke_timer_t booke_timer_t;
64struct booke_timer_t {
65
66 uint64_t fit_next;
67 QEMUTimer *fit_timer;
68
69 uint64_t wdt_next;

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62
63typedef struct booke_timer_t booke_timer_t;
64struct booke_timer_t {
65
66 uint64_t fit_next;
67 QEMUTimer *fit_timer;
68
69 uint64_t wdt_next;

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