pnv.c (4f9924c4d4cf9c039e247c5cdbbf71bce4e573c3) pnv.c (9ae1329ee2fee95f201ca219090d7c742eaf6a90)
1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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611static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
612{
613 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
614}
615
616static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
617{
618 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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611static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
612{
613 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
614}
615
616static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
617{
618 Pnv8Chip *chip8 = PNV8_CHIP(chip);
619 int i;
619
620 ics_pic_print_info(&chip8->psi.ics, mon);
620
621 ics_pic_print_info(&chip8->psi.ics, mon);
622 for (i = 0; i < chip->num_phbs; i++) {
623 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
624 ics_pic_print_info(&chip8->phbs[i].lsis, mon);
625 }
621}
622
623static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
624{
625 Pnv9Chip *chip9 = PNV9_CHIP(chip);
626 int i, j;
627
628 pnv_xive_pic_print_info(&chip9->xive, mon);

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1021 */
1022#define POWER9_CORE_MASK (0xffffffffffffffull)
1023
1024
1025#define POWER10_CORE_MASK (0xffffffffffffffull)
1026
1027static void pnv_chip_power8_instance_init(Object *obj)
1028{
626}
627
628static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
629{
630 Pnv9Chip *chip9 = PNV9_CHIP(chip);
631 int i, j;
632
633 pnv_xive_pic_print_info(&chip9->xive, mon);

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1026 */
1027#define POWER9_CORE_MASK (0xffffffffffffffull)
1028
1029
1030#define POWER10_CORE_MASK (0xffffffffffffffull)
1031
1032static void pnv_chip_power8_instance_init(Object *obj)
1033{
1034 PnvChip *chip = PNV_CHIP(obj);
1029 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1035 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1036 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1037 int i;
1030
1031 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1032 (Object **)&chip8->xics,
1033 object_property_allow_set_link,
1034 OBJ_PROP_LINK_STRONG,
1035 &error_abort);
1036
1037 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
1038 TYPE_PNV8_PSI, &error_abort, NULL);
1039
1040 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
1041 TYPE_PNV8_LPC, &error_abort, NULL);
1042
1043 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
1044 TYPE_PNV8_OCC, &error_abort, NULL);
1045
1046 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1047 TYPE_PNV8_HOMER, &error_abort, NULL);
1038
1039 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1040 (Object **)&chip8->xics,
1041 object_property_allow_set_link,
1042 OBJ_PROP_LINK_STRONG,
1043 &error_abort);
1044
1045 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
1046 TYPE_PNV8_PSI, &error_abort, NULL);
1047
1048 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
1049 TYPE_PNV8_LPC, &error_abort, NULL);
1050
1051 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
1052 TYPE_PNV8_OCC, &error_abort, NULL);
1053
1054 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1055 TYPE_PNV8_HOMER, &error_abort, NULL);
1056
1057 for (i = 0; i < pcc->num_phbs; i++) {
1058 object_initialize_child(obj, "phb[*]", &chip8->phbs[i],
1059 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3,
1060 &error_abort, NULL);
1061 }
1062
1063 /*
1064 * Number of PHBs is the chip default
1065 */
1066 chip->num_phbs = pcc->num_phbs;
1048}
1049
1050static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1051 {
1052 PnvChip *chip = PNV_CHIP(chip8);
1053 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1054 int i, j;
1055 char *name;

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1078
1079static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1080{
1081 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1082 PnvChip *chip = PNV_CHIP(dev);
1083 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1084 Pnv8Psi *psi8 = &chip8->psi;
1085 Error *local_err = NULL;
1067}
1068
1069static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1070 {
1071 PnvChip *chip = PNV_CHIP(chip8);
1072 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1073 int i, j;
1074 char *name;

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1097
1098static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1099{
1100 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1101 PnvChip *chip = PNV_CHIP(dev);
1102 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1103 Pnv8Psi *psi8 = &chip8->psi;
1104 Error *local_err = NULL;
1105 int i;
1086
1087 assert(chip8->xics);
1088
1089 /* XSCOM bridge is first */
1090 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1091 if (local_err) {
1092 error_propagate(errp, local_err);
1093 return;

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1158 return;
1159 }
1160 /* Homer Xscom region */
1161 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1162
1163 /* Homer mmio region */
1164 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1165 &chip8->homer.regs);
1106
1107 assert(chip8->xics);
1108
1109 /* XSCOM bridge is first */
1110 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1111 if (local_err) {
1112 error_propagate(errp, local_err);
1113 return;

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1178 return;
1179 }
1180 /* Homer Xscom region */
1181 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1182
1183 /* Homer mmio region */
1184 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1185 &chip8->homer.regs);
1186
1187 /* PHB3 controllers */
1188 for (i = 0; i < chip->num_phbs; i++) {
1189 PnvPHB3 *phb = &chip8->phbs[i];
1190 PnvPBCQState *pbcq = &phb->pbcq;
1191
1192 object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
1193 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
1194 &error_fatal);
1195 object_property_set_bool(OBJECT(phb), true, "realized", &local_err);
1196 if (local_err) {
1197 error_propagate(errp, local_err);
1198 return;
1199 }
1200 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default());
1201
1202 /* Populate the XSCOM address space. */
1203 pnv_xscom_add_subregion(chip,
1204 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
1205 &pbcq->xscom_nest_regs);
1206 pnv_xscom_add_subregion(chip,
1207 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
1208 &pbcq->xscom_pci_regs);
1209 pnv_xscom_add_subregion(chip,
1210 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
1211 &pbcq->xscom_spci_regs);
1212 }
1166}
1167
1168static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1169{
1170 addr &= (PNV_XSCOM_SIZE - 1);
1171 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1172}
1173
1174static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1175{
1176 DeviceClass *dc = DEVICE_CLASS(klass);
1177 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1178
1179 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1180 k->cores_mask = POWER8E_CORE_MASK;
1213}
1214
1215static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1216{
1217 addr &= (PNV_XSCOM_SIZE - 1);
1218 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1219}
1220
1221static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1222{
1223 DeviceClass *dc = DEVICE_CLASS(klass);
1224 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1225
1226 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1227 k->cores_mask = POWER8E_CORE_MASK;
1228 k->num_phbs = 3;
1181 k->core_pir = pnv_chip_core_pir_p8;
1182 k->intc_create = pnv_chip_power8_intc_create;
1183 k->intc_reset = pnv_chip_power8_intc_reset;
1184 k->intc_destroy = pnv_chip_power8_intc_destroy;
1185 k->intc_print_info = pnv_chip_power8_intc_print_info;
1186 k->isa_create = pnv_chip_power8_isa_create;
1187 k->dt_populate = pnv_chip_power8_dt_populate;
1188 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1196
1197static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1198{
1199 DeviceClass *dc = DEVICE_CLASS(klass);
1200 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1201
1202 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1203 k->cores_mask = POWER8_CORE_MASK;
1229 k->core_pir = pnv_chip_core_pir_p8;
1230 k->intc_create = pnv_chip_power8_intc_create;
1231 k->intc_reset = pnv_chip_power8_intc_reset;
1232 k->intc_destroy = pnv_chip_power8_intc_destroy;
1233 k->intc_print_info = pnv_chip_power8_intc_print_info;
1234 k->isa_create = pnv_chip_power8_isa_create;
1235 k->dt_populate = pnv_chip_power8_dt_populate;
1236 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1244
1245static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1246{
1247 DeviceClass *dc = DEVICE_CLASS(klass);
1248 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1249
1250 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1251 k->cores_mask = POWER8_CORE_MASK;
1252 k->num_phbs = 3;
1204 k->core_pir = pnv_chip_core_pir_p8;
1205 k->intc_create = pnv_chip_power8_intc_create;
1206 k->intc_reset = pnv_chip_power8_intc_reset;
1207 k->intc_destroy = pnv_chip_power8_intc_destroy;
1208 k->intc_print_info = pnv_chip_power8_intc_print_info;
1209 k->isa_create = pnv_chip_power8_isa_create;
1210 k->dt_populate = pnv_chip_power8_dt_populate;
1211 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1219
1220static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1221{
1222 DeviceClass *dc = DEVICE_CLASS(klass);
1223 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1224
1225 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1226 k->cores_mask = POWER8_CORE_MASK;
1253 k->core_pir = pnv_chip_core_pir_p8;
1254 k->intc_create = pnv_chip_power8_intc_create;
1255 k->intc_reset = pnv_chip_power8_intc_reset;
1256 k->intc_destroy = pnv_chip_power8_intc_destroy;
1257 k->intc_print_info = pnv_chip_power8_intc_print_info;
1258 k->isa_create = pnv_chip_power8_isa_create;
1259 k->dt_populate = pnv_chip_power8_dt_populate;
1260 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1268
1269static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1270{
1271 DeviceClass *dc = DEVICE_CLASS(klass);
1272 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1273
1274 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1275 k->cores_mask = POWER8_CORE_MASK;
1276 k->num_phbs = 3;
1227 k->core_pir = pnv_chip_core_pir_p8;
1228 k->intc_create = pnv_chip_power8_intc_create;
1229 k->intc_reset = pnv_chip_power8_intc_reset;
1230 k->intc_destroy = pnv_chip_power8_intc_destroy;
1231 k->intc_print_info = pnv_chip_power8_intc_print_info;
1232 k->isa_create = pnv_chip_power8nvl_isa_create;
1233 k->dt_populate = pnv_chip_power8_dt_populate;
1234 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1743 }
1744 }
1745 return NULL;
1746}
1747
1748static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1749{
1750 PnvMachineState *pnv = PNV_MACHINE(xi);
1277 k->core_pir = pnv_chip_core_pir_p8;
1278 k->intc_create = pnv_chip_power8_intc_create;
1279 k->intc_reset = pnv_chip_power8_intc_reset;
1280 k->intc_destroy = pnv_chip_power8_intc_destroy;
1281 k->intc_print_info = pnv_chip_power8_intc_print_info;
1282 k->isa_create = pnv_chip_power8nvl_isa_create;
1283 k->dt_populate = pnv_chip_power8_dt_populate;
1284 k->pic_print_info = pnv_chip_power8_pic_print_info;

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1793 }
1794 }
1795 return NULL;
1796}
1797
1798static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1799{
1800 PnvMachineState *pnv = PNV_MACHINE(xi);
1751 int i;
1801 int i, j;
1752
1753 for (i = 0; i < pnv->num_chips; i++) {
1802
1803 for (i = 0; i < pnv->num_chips; i++) {
1804 PnvChip *chip = pnv->chips[i];
1754 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1755
1756 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1757 return &chip8->psi.ics;
1758 }
1805 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1806
1807 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1808 return &chip8->psi.ics;
1809 }
1810 for (j = 0; j < chip->num_phbs; j++) {
1811 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
1812 return &chip8->phbs[j].lsis;
1813 }
1814 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
1815 return ICS(&chip8->phbs[j].msis);
1816 }
1817 }
1759 }
1760 return NULL;
1761}
1762
1763static void pnv_ics_resend(XICSFabric *xi)
1764{
1765 PnvMachineState *pnv = PNV_MACHINE(xi);
1818 }
1819 return NULL;
1820}
1821
1822static void pnv_ics_resend(XICSFabric *xi)
1823{
1824 PnvMachineState *pnv = PNV_MACHINE(xi);
1766 int i;
1825 int i, j;
1767
1768 for (i = 0; i < pnv->num_chips; i++) {
1826
1827 for (i = 0; i < pnv->num_chips; i++) {
1828 PnvChip *chip = pnv->chips[i];
1769 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1829 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1830
1770 ics_resend(&chip8->psi.ics);
1831 ics_resend(&chip8->psi.ics);
1832 for (j = 0; j < chip->num_phbs; j++) {
1833 ics_resend(&chip8->phbs[j].lsis);
1834 ics_resend(ICS(&chip8->phbs[j].msis));
1835 }
1771 }
1772}
1773
1774static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1775{
1776 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1777
1778 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;

--- 249 unchanged lines hidden --- 		1836 }
1837}
1838
1839static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1840{
1841 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1842
1843 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;

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