e500.c (6d4e18925a65306afabaad7b63a4588c18919e99) e500.c (a2cb15b0ddfa05f81a42d7b65dd0c7c50e420c33)
1/*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include "config.h"
18#include "qemu-common.h"
19#include "e500.h"
1/*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include "config.h"
18#include "qemu-common.h"
19#include "e500.h"
20#include "e500-ccsr.h"
21#include "net.h"
22#include "hw/hw.h"
23#include "hw/serial.h"
20#include "net.h"
21#include "hw/hw.h"
22#include "hw/serial.h"
24#include "hw/pci.h"
23#include "hw/pci/pci.h"
25#include "hw/boards.h"
26#include "sysemu.h"
27#include "kvm.h"
28#include "kvm_ppc.h"
29#include "device_tree.h"
30#include "hw/openpic.h"
31#include "hw/ppc.h"
32#include "hw/loader.h"
33#include "elf.h"
34#include "hw/sysbus.h"
35#include "exec-memory.h"
36#include "host-utils.h"
24#include "hw/boards.h"
25#include "sysemu.h"
26#include "kvm.h"
27#include "kvm_ppc.h"
28#include "device_tree.h"
29#include "hw/openpic.h"
30#include "hw/ppc.h"
31#include "hw/loader.h"
32#include "elf.h"
33#include "hw/sysbus.h"
34#include "exec-memory.h"
35#include "host-utils.h"
37#include "hw/ppce500_pci.h"
38
39#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
40#define UIMAGE_LOAD_BASE 0
41#define DTC_LOAD_PAD 0x1800000
42#define DTC_PAD_MASK 0xFFFFF
43#define INITRD_LOAD_PAD 0x2000000
44#define INITRD_PAD_MASK 0xFFFFFF
45
46#define RAM_SIZES_ALIGN (64UL << 20)
47
48/* TODO: parameterize */
49#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
50#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
36
37#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
38#define UIMAGE_LOAD_BASE 0
39#define DTC_LOAD_PAD 0x1800000
40#define DTC_PAD_MASK 0xFFFFF
41#define INITRD_LOAD_PAD 0x2000000
42#define INITRD_PAD_MASK 0xFFFFFF
43
44#define RAM_SIZES_ALIGN (64UL << 20)
45
46/* TODO: parameterize */
47#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
48#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
51#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
52#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
53#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
54#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
55#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
56#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
57 MPC8544_PCI_REGS_OFFSET)
49#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000ULL)
50#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500ULL)
51#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600ULL)
52#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL)
58#define MPC8544_PCI_REGS_SIZE 0x1000ULL
59#define MPC8544_PCI_IO 0xE1000000ULL
53#define MPC8544_PCI_REGS_SIZE 0x1000ULL
54#define MPC8544_PCI_IO 0xE1000000ULL
60#define MPC8544_UTIL_OFFSET 0xe0000ULL
55#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
61#define MPC8544_SPIN_BASE 0xEF000000ULL
62
63struct boot_info
64{
65 uint32_t dt_base;
66 uint32_t dt_size;
67 uint32_t entry;
68};
69
56#define MPC8544_SPIN_BASE 0xEF000000ULL
57
58struct boot_info
59{
60 uint32_t dt_base;
61 uint32_t dt_size;
62 uint32_t entry;
63};
64
70static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
71 int nr_slots, int *len)
65static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
72{
66{
73 int i = 0;
74 int slot;
75 int pci_irq;
76 int host_irq;
77 int last_slot = first_slot + nr_slots;
78 uint32_t *pci_map;
67 int i;
68 const uint32_t tmp[] = {
69 /* IDSEL 0x11 J17 Slot 1 */
70 0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1,
71 0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1,
72 0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1,
73 0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
79
74
80 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
81 pci_map = g_malloc(*len);
82
83 for (slot = first_slot; slot < last_slot; slot++) {
84 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
85 pci_map[i++] = cpu_to_be32(slot << 11);
86 pci_map[i++] = cpu_to_be32(0x0);
87 pci_map[i++] = cpu_to_be32(0x0);
88 pci_map[i++] = cpu_to_be32(pci_irq + 1);
89 pci_map[i++] = cpu_to_be32(mpic);
90 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
91 pci_map[i++] = cpu_to_be32(host_irq + 1);
92 pci_map[i++] = cpu_to_be32(0x1);
93 }
75 /* IDSEL 0x12 J16 Slot 2 */
76 0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1,
77 0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1,
78 0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1,
79 0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
80 };
81 for (i = 0; i < (7 * 8); i++) {
82 pci_map[i] = cpu_to_be32(tmp[i]);
94 }
83 }
95
96 assert((i * sizeof(uint32_t)) == *len);
97
98 return pci_map;
99}
100
101static void dt_serial_create(void *fdt, unsigned long long offset,
102 const char *soc, const char *mpic,
103 const char *alias, int idx, bool defcon)
104{
105 char ser[128];
106

--- 27 unchanged lines hidden (view full) ---

134 uint32_t clock_freq = 400000000;
135 uint32_t tb_freq = 400000000;
136 int i;
137 const char *toplevel_compat = NULL; /* user override */
138 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
139 char soc[128];
140 char mpic[128];
141 uint32_t mpic_ph;
84}
85
86static void dt_serial_create(void *fdt, unsigned long long offset,
87 const char *soc, const char *mpic,
88 const char *alias, int idx, bool defcon)
89{
90 char ser[128];
91

--- 27 unchanged lines hidden (view full) ---

119 uint32_t clock_freq = 400000000;
120 uint32_t tb_freq = 400000000;
121 int i;
122 const char *toplevel_compat = NULL; /* user override */
123 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
124 char soc[128];
125 char mpic[128];
126 uint32_t mpic_ph;
142 uint32_t msi_ph;
143 char gutil[128];
144 char pci[128];
127 char gutil[128];
128 char pci[128];
145 char msi[128];
146 uint32_t *pci_map = NULL;
147 int len;
129 uint32_t pci_map[7 * 8];
148 uint32_t pci_ranges[14] =
149 {
150 0x2000000, 0x0, 0xc0000000,
151 0x0, 0xc0000000,
152 0x0, 0x20000000,
153
154 0x1000000, 0x0, 0x0,
155 0x0, 0xe1000000,

--- 124 unchanged lines hidden (view full) ---

280 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
281 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
282 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
283 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
284 MPC8544_CCSRBAR_SIZE);
285 /* XXX should contain a reasonable value */
286 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
287
130 uint32_t pci_ranges[14] =
131 {
132 0x2000000, 0x0, 0xc0000000,
133 0x0, 0xc0000000,
134 0x0, 0x20000000,
135
136 0x1000000, 0x0, 0x0,
137 0x0, 0xe1000000,

--- 124 unchanged lines hidden (view full) ---

262 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
263 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
264 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
265 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
266 MPC8544_CCSRBAR_SIZE);
267 /* XXX should contain a reasonable value */
268 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
269
288 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
270 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc,
271 MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);
289 qemu_devtree_add_subnode(fdt, mpic);
290 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
291 qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
272 qemu_devtree_add_subnode(fdt, mpic);
273 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
274 qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
292 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
293 0x40000);
275 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -
276 MPC8544_CCSRBAR_BASE, 0x40000);
294 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
295 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
296 mpic_ph = qemu_devtree_alloc_phandle(fdt);
297 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
298 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
299 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
300
301 /*
302 * We have to generate ser1 first, because Linux takes the first
303 * device it finds in the dt as serial output device. And we generate
304 * devices in reverse order to the dt.
305 */
277 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
278 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
279 mpic_ph = qemu_devtree_alloc_phandle(fdt);
280 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
281 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
282 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
283
284 /*
285 * We have to generate ser1 first, because Linux takes the first
286 * device it finds in the dt as serial output device. And we generate
287 * devices in reverse order to the dt.
288 */
306 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
289 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE,
307 soc, mpic, "serial1", 1, false);
290 soc, mpic, "serial1", 1, false);
308 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
291 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE,
309 soc, mpic, "serial0", 0, true);
310
311 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
292 soc, mpic, "serial0", 0, true);
293
294 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
312 MPC8544_UTIL_OFFSET);
295 MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);
313 qemu_devtree_add_subnode(fdt, gutil);
314 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
296 qemu_devtree_add_subnode(fdt, gutil);
297 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
315 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
298 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -
299 MPC8544_CCSRBAR_BASE, 0x1000);
316 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
317
300 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
301
318 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
319 qemu_devtree_add_subnode(fdt, msi);
320 qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
321 qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
322 msi_ph = qemu_devtree_alloc_phandle(fdt);
323 qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
324 qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
325 qemu_devtree_setprop_cells(fdt, msi, "interrupts",
326 0xe0, 0x0,
327 0xe1, 0x0,
328 0xe2, 0x0,
329 0xe3, 0x0,
330 0xe4, 0x0,
331 0xe5, 0x0,
332 0xe6, 0x0,
333 0xe7, 0x0);
334 qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
335 qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
336
337 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
338 qemu_devtree_add_subnode(fdt, pci);
339 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
340 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
341 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
342 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
343 0x0, 0x7);
302 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
303 qemu_devtree_add_subnode(fdt, pci);
304 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
305 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
306 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
307 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
308 0x0, 0x7);
344 pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
345 params->pci_first_slot, params->pci_nr_slots,
346 &len);
347 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
309 pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
310 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));
348 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
349 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
350 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
351 for (i = 0; i < 14; i++) {
352 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
353 }
311 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
312 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
313 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
314 for (i = 0; i < 14; i++) {
315 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
316 }
354 qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
355 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
356 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
357 MPC8544_PCI_REGS_BASE, 0, 0x1000);
358 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
359 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
360 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
361 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
362 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);

--- 10 unchanged lines hidden (view full) ---

373 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
374 if (ret < 0) {
375 goto out;
376 }
377 g_free(fdt);
378 ret = fdt_size;
379
380out:
317 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
318 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
319 MPC8544_PCI_REGS_BASE, 0, 0x1000);
320 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
321 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
322 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
323 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
324 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);

--- 10 unchanged lines hidden (view full) ---

335 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
336 if (ret < 0) {
337 goto out;
338 }
339 g_free(fdt);
340 ret = fdt_size;
341
342out:
381 g_free(pci_map);
382
383 return ret;
384}
385
386/* Create -kernel TLB entries for BookE. */
387static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
388{
389 return 63 - clz64(size >> 10);

--- 61 unchanged lines hidden (view full) ---

451 uint64_t elf_entry;
452 uint64_t elf_lowaddr;
453 hwaddr entry=0;
454 hwaddr loadaddr=UIMAGE_LOAD_BASE;
455 target_long kernel_size=0;
456 target_ulong dt_base = 0;
457 target_ulong initrd_base = 0;
458 target_long initrd_size=0;
343
344 return ret;
345}
346
347/* Create -kernel TLB entries for BookE. */
348static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
349{
350 return 63 - clz64(size >> 10);

--- 61 unchanged lines hidden (view full) ---

412 uint64_t elf_entry;
413 uint64_t elf_lowaddr;
414 hwaddr entry=0;
415 hwaddr loadaddr=UIMAGE_LOAD_BASE;
416 target_long kernel_size=0;
417 target_ulong dt_base = 0;
418 target_ulong initrd_base = 0;
419 target_long initrd_size=0;
459 int i = 0, j, k;
420 int i=0;
460 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
461 qemu_irq **irqs, *mpic;
462 DeviceState *dev;
463 CPUPPCState *firstenv = NULL;
421 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
422 qemu_irq **irqs, *mpic;
423 DeviceState *dev;
424 CPUPPCState *firstenv = NULL;
464 MemoryRegion *ccsr_addr_space;
465 SysBusDevice *s;
466 PPCE500CCSRState *ccsr;
467
468 /* Setup CPUs */
469 if (params->cpu_model == NULL) {
470 params->cpu_model = "e500v2_v30";
471 }
472
473 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
474 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);

--- 12 unchanged lines hidden (view full) ---

487 firstenv = env;
488 }
489
490 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
491 input = (qemu_irq *)env->irq_inputs;
492 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
493 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
494 env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
425
426 /* Setup CPUs */
427 if (params->cpu_model == NULL) {
428 params->cpu_model = "e500v2_v30";
429 }
430
431 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
432 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);

--- 12 unchanged lines hidden (view full) ---

445 firstenv = env;
446 }
447
448 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
449 input = (qemu_irq *)env->irq_inputs;
450 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
451 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
452 env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
495 env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
496 MPC8544_MPIC_REGS_OFFSET + 0x20000;
453 env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000;
497
498 ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
499
500 /* Register reset handler */
501 if (!i) {
502 /* Primary CPU */
503 struct boot_info *boot_info;
504 boot_info = g_malloc0(sizeof(struct boot_info));

--- 10 unchanged lines hidden (view full) ---

515 /* Fixup Memory size on a alignment boundary */
516 ram_size &= ~(RAM_SIZES_ALIGN - 1);
517
518 /* Register Memory */
519 memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
520 vmstate_register_ram_global(ram);
521 memory_region_add_subregion(address_space_mem, 0, ram);
522
454
455 ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
456
457 /* Register reset handler */
458 if (!i) {
459 /* Primary CPU */
460 struct boot_info *boot_info;
461 boot_info = g_malloc0(sizeof(struct boot_info));

--- 10 unchanged lines hidden (view full) ---

472 /* Fixup Memory size on a alignment boundary */
473 ram_size &= ~(RAM_SIZES_ALIGN - 1);
474
475 /* Register Memory */
476 memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
477 vmstate_register_ram_global(ram);
478 memory_region_add_subregion(address_space_mem, 0, ram);
479
523 dev = qdev_create(NULL, "e500-ccsr");
524 object_property_add_child(qdev_get_machine(), "e500-ccsr",
525 OBJECT(dev), NULL);
526 qdev_init_nofail(dev);
527 ccsr = CCSR(dev);
528 ccsr_addr_space = &ccsr->ccsr_space;
529 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
530 ccsr_addr_space);
531
532 /* MPIC */
480 /* MPIC */
533 mpic = g_new(qemu_irq, 256);
534 dev = qdev_create(NULL, "openpic");
535 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
536 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
537 qdev_init_nofail(dev);
538 s = sysbus_from_qdev(dev);
481 mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
482 smp_cpus, irqs, NULL);
539
483
540 k = 0;
541 for (i = 0; i < smp_cpus; i++) {
542 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
543 sysbus_connect_irq(s, k++, irqs[i][j]);
544 }
484 if (!mpic) {
485 cpu_abort(env, "MPIC failed to initialize\n");
545 }
546
486 }
487
547 for (i = 0; i < 256; i++) {
548 mpic[i] = qdev_get_gpio_in(dev, i);
549 }
550
551 memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
552 s->mmio[0].memory);
553
554 /* Serial */
555 if (serial_hds[0]) {
488 /* Serial */
489 if (serial_hds[0]) {
556 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
557 0, mpic[42], 399193,
490 serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
491 0, mpic[12+26], 399193,
558 serial_hds[0], DEVICE_BIG_ENDIAN);
559 }
560
561 if (serial_hds[1]) {
492 serial_hds[0], DEVICE_BIG_ENDIAN);
493 }
494
495 if (serial_hds[1]) {
562 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
563 0, mpic[42], 399193,
496 serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
497 0, mpic[12+26], 399193,
564 serial_hds[1], DEVICE_BIG_ENDIAN);
565 }
566
567 /* General Utility device */
498 serial_hds[1], DEVICE_BIG_ENDIAN);
499 }
500
501 /* General Utility device */
568 dev = qdev_create(NULL, "mpc8544-guts");
569 qdev_init_nofail(dev);
570 s = SYS_BUS_DEVICE(dev);
571 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
572 sysbus_mmio_get_region(s, 0));
502 sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
573
574 /* PCI */
503
504 /* PCI */
575 dev = qdev_create(NULL, "e500-pcihost");
576 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
577 qdev_init_nofail(dev);
578 s = SYS_BUS_DEVICE(dev);
579 sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
580 sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
581 sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
582 sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
583 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
584 sysbus_mmio_get_region(s, 0));
585
505 dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
506 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
507 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
508 NULL);
586 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
587 if (!pci_bus)
588 printf("couldn't create PCI controller!\n");
589
590 sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
591
592 if (pci_bus) {
593 /* Register network interfaces. */

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650 boot_info->dt_base = dt_base;
651 boot_info->dt_size = dt_size;
652 }
653
654 if (kvm_enabled()) {
655 kvmppc_init();
656 }
657}
509 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
510 if (!pci_bus)
511 printf("couldn't create PCI controller!\n");
512
513 sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
514
515 if (pci_bus) {
516 /* Register network interfaces. */

--- 56 unchanged lines hidden (view full) ---

573 boot_info->dt_base = dt_base;
574 boot_info->dt_size = dt_size;
575 }
576
577 if (kvm_enabled()) {
578 kvmppc_init();
579 }
580}
658
659static int e500_ccsr_initfn(SysBusDevice *dev)
660{
661 PPCE500CCSRState *ccsr;
662
663 ccsr = CCSR(dev);
664 memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
665 MPC8544_CCSRBAR_SIZE);
666 return 0;
667}
668
669static void e500_ccsr_class_init(ObjectClass *klass, void *data)
670{
671 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
672 k->init = e500_ccsr_initfn;
673}
674
675static const TypeInfo e500_ccsr_info = {
676 .name = TYPE_CCSR,
677 .parent = TYPE_SYS_BUS_DEVICE,
678 .instance_size = sizeof(PPCE500CCSRState),
679 .class_init = e500_ccsr_class_init,
680};
681
682static void e500_register_types(void)
683{
684 type_register_static(&e500_ccsr_info);
685}
686
687type_init(e500_register_types)