pci.c (b019f5e5375224a003f260c89d424fea7767b7fc) pci.c (727b48661f757678f7f42f557ddac072c5a49721)
1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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1348 }
1349}
1350
1351uint32_t pci_default_read_config(PCIDevice *d,
1352 uint32_t address, int len)
1353{
1354 uint32_t val = 0;
1355
1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

--- 1339 unchanged lines hidden (view full) ---

1348 }
1349}
1350
1351uint32_t pci_default_read_config(PCIDevice *d,
1352 uint32_t address, int len)
1353{
1354 uint32_t val = 0;
1355
1356 if (pci_is_express_downstream_port(d) &&
1357 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1358 pcie_sync_bridge_lnk(d);
1359 }
1356 memcpy(&val, d->config + address, len);
1357 return le32_to_cpu(val);
1358}
1359
1360void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1361{
1362 int i, was_irq_disabled = pci_irq_disabled(d);
1363 uint32_t val = val_in;

--- 1330 unchanged lines hidden --- 		1360 memcpy(&val, d->config + address, len);
1361 return le32_to_cpu(val);
1362}
1363
1364void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1365{
1366 int i, was_irq_disabled = pci_irq_disabled(d);
1367 uint32_t val = val_in;

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