openrisc_sim.c (ffa4822c015d5670ef6a2239f3cbd2ff2cec57de) openrisc_sim.c (e264d29de28c5b0be3d063307ce9fb613b427cc3)
1/*
2 * OpenRISC simulator for use as an IIS.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 118 unchanged lines hidden (view full) ---

127 if (nd_table[0].used) {
128 openrisc_sim_net_init(get_system_memory(), 0x92000000,
129 0x92000400, cpu->env.irq[4], nd_table);
130 }
131
132 cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
133}
134
1/*
2 * OpenRISC simulator for use as an IIS.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 118 unchanged lines hidden (view full) ---

127 if (nd_table[0].used) {
128 openrisc_sim_net_init(get_system_memory(), 0x92000000,
129 0x92000400, cpu->env.irq[4], nd_table);
130 }
131
132 cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
133}
134
135static QEMUMachine openrisc_sim_machine = {
136 .name = "or32-sim",
137 .desc = "or32 simulation",
138 .init = openrisc_sim_init,
139 .max_cpus = 1,
140 .is_default = 1,
141};
142
143static void openrisc_sim_machine_init(void)
135static void openrisc_sim_machine_init(MachineClass *mc)
144{
136{
145 qemu_register_machine(&openrisc_sim_machine);
137 mc->desc = "or32 simulation";
138 mc->init = openrisc_sim_init;
139 mc->max_cpus = 1;
140 mc->is_default = 1;
146}
147
141}
142
148machine_init(openrisc_sim_machine_init);
143DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init)