openrisc_sim.c (17a5bbb44df9a4a79166332bc26e2d8ca6bd8fa8) openrisc_sim.c (9bca0edb282de0007a4f068d9d20f3e3c3aadef7)
1/*
2 * OpenRISC simulator for use as an IIS.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 150 unchanged lines hidden (view full) ---

159 openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
160
161 serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
162 } else {
163 serial_irq = cpu_irqs[0][2];
164 }
165
166 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
1/*
2 * OpenRISC simulator for use as an IIS.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public

--- 150 unchanged lines hidden (view full) ---

159 openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
160
161 serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
162 } else {
163 serial_irq = cpu_irqs[0][2];
164 }
165
166 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
167 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
167 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
168
169 openrisc_load_kernel(ram_size, kernel_filename);
170}
171
172static void openrisc_sim_machine_init(MachineClass *mc)
173{
174 mc->desc = "or1k simulation";
175 mc->init = openrisc_sim_init;
176 mc->max_cpus = 2;
177 mc->is_default = 1;
178 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
179}
180
181DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
168
169 openrisc_load_kernel(ram_size, kernel_filename);
170}
171
172static void openrisc_sim_machine_init(MachineClass *mc)
173{
174 mc->desc = "or1k simulation";
175 mc->init = openrisc_sim_init;
176 mc->max_cpus = 2;
177 mc->is_default = 1;
178 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
179}
180
181DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)