ctrl.c (a555af1707be7f564320cbb444ef68448ff16549) ctrl.c (771dbc3ac484af35cddf7e4971e66a1fd1a07156)
1/*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.

--- 4440 unchanged lines hidden (view full) ---

4449
4450 if (!rae) {
4451 nvme_clear_events(n, NVME_AER_TYPE_SMART);
4452 }
4453
4454 return nvme_c2h(n, (uint8_t *) &smart + off, trans_len, req);
4455}
4456
1/*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.

--- 4440 unchanged lines hidden (view full) ---

4449
4450 if (!rae) {
4451 nvme_clear_events(n, NVME_AER_TYPE_SMART);
4452 }
4453
4454 return nvme_c2h(n, (uint8_t *) &smart + off, trans_len, req);
4455}
4456
4457static uint16_t nvme_endgrp_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
4458 uint64_t off, NvmeRequest *req)
4459{
4460 uint32_t dw11 = le32_to_cpu(req->cmd.cdw11);
4461 uint16_t endgrpid = (dw11 >> 16) & 0xffff;
4462 struct nvme_stats stats = {};
4463 NvmeEndGrpLog info = {};
4464 int i;
4465
4466 if (!n->subsys || endgrpid != 0x1) {
4467 return NVME_INVALID_FIELD | NVME_DNR;
4468 }
4469
4470 if (off >= sizeof(info)) {
4471 return NVME_INVALID_FIELD | NVME_DNR;
4472 }
4473
4474 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
4475 NvmeNamespace *ns = nvme_subsys_ns(n->subsys, i);
4476 if (!ns) {
4477 continue;
4478 }
4479
4480 nvme_set_blk_stats(ns, &stats);
4481 }
4482
4483 info.data_units_read[0] =
4484 cpu_to_le64(DIV_ROUND_UP(stats.units_read / 1000000000, 1000000000));
4485 info.data_units_written[0] =
4486 cpu_to_le64(DIV_ROUND_UP(stats.units_written / 1000000000, 1000000000));
4487 info.media_units_written[0] =
4488 cpu_to_le64(DIV_ROUND_UP(stats.units_written / 1000000000, 1000000000));
4489
4490 info.host_read_commands[0] = cpu_to_le64(stats.read_commands);
4491 info.host_write_commands[0] = cpu_to_le64(stats.write_commands);
4492
4493 buf_len = MIN(sizeof(info) - off, buf_len);
4494
4495 return nvme_c2h(n, (uint8_t *)&info + off, buf_len, req);
4496}
4497
4498
4457static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
4458 NvmeRequest *req)
4459{
4460 uint32_t trans_len;
4461 NvmeFwSlotInfoLog fw_log = {
4462 .afi = 0x1,
4463 };
4464

--- 156 unchanged lines hidden (view full) ---

4621 case NVME_LOG_SMART_INFO:
4622 return nvme_smart_info(n, rae, len, off, req);
4623 case NVME_LOG_FW_SLOT_INFO:
4624 return nvme_fw_log_info(n, len, off, req);
4625 case NVME_LOG_CHANGED_NSLIST:
4626 return nvme_changed_nslist(n, rae, len, off, req);
4627 case NVME_LOG_CMD_EFFECTS:
4628 return nvme_cmd_effects(n, csi, len, off, req);
4499static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
4500 NvmeRequest *req)
4501{
4502 uint32_t trans_len;
4503 NvmeFwSlotInfoLog fw_log = {
4504 .afi = 0x1,
4505 };
4506

--- 156 unchanged lines hidden (view full) ---

4663 case NVME_LOG_SMART_INFO:
4664 return nvme_smart_info(n, rae, len, off, req);
4665 case NVME_LOG_FW_SLOT_INFO:
4666 return nvme_fw_log_info(n, len, off, req);
4667 case NVME_LOG_CHANGED_NSLIST:
4668 return nvme_changed_nslist(n, rae, len, off, req);
4669 case NVME_LOG_CMD_EFFECTS:
4670 return nvme_cmd_effects(n, csi, len, off, req);
4671 case NVME_LOG_ENDGRP:
4672 return nvme_endgrp_info(n, rae, len, off, req);
4629 default:
4630 trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
4631 return NVME_INVALID_FIELD | NVME_DNR;
4632 }
4633}
4634
4635static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
4636{

--- 2740 unchanged lines hidden (view full) ---

7377}
7378
7379static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
7380{
7381 NvmeIdCtrl *id = &n->id_ctrl;
7382 uint8_t *pci_conf = pci_dev->config;
7383 uint64_t cap = ldq_le_p(&n->bar.cap);
7384 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
4673 default:
4674 trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
4675 return NVME_INVALID_FIELD | NVME_DNR;
4676 }
4677}
4678
4679static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
4680{

--- 2740 unchanged lines hidden (view full) ---

7421}
7422
7423static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
7424{
7425 NvmeIdCtrl *id = &n->id_ctrl;
7426 uint8_t *pci_conf = pci_dev->config;
7427 uint64_t cap = ldq_le_p(&n->bar.cap);
7428 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
7429 uint32_t ctratt;
7385
7386 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
7387 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
7388 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
7389 strpadcpy((char *)id->fr, sizeof(id->fr), QEMU_VERSION, ' ');
7390 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
7391
7392 id->cntlid = cpu_to_le16(n->cntlid);
7393
7394 id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
7430
7431 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
7432 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
7433 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
7434 strpadcpy((char *)id->fr, sizeof(id->fr), QEMU_VERSION, ' ');
7435 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
7436
7437 id->cntlid = cpu_to_le16(n->cntlid);
7438
7439 id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
7395 id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS);
7440 ctratt = NVME_CTRATT_ELBAS;
7396
7397 id->rab = 6;
7398
7399 if (n->params.use_intel_id) {
7400 id->ieee[0] = 0xb3;
7401 id->ieee[1] = 0x02;
7402 id->ieee[2] = 0x00;
7403 } else {

--- 50 unchanged lines hidden (view full) ---

7454 nvme_init_subnqn(n);
7455
7456 id->psd[0].mp = cpu_to_le16(0x9c4);
7457 id->psd[0].enlat = cpu_to_le32(0x10);
7458 id->psd[0].exlat = cpu_to_le32(0x4);
7459
7460 if (n->subsys) {
7461 id->cmic |= NVME_CMIC_MULTI_CTRL;
7441
7442 id->rab = 6;
7443
7444 if (n->params.use_intel_id) {
7445 id->ieee[0] = 0xb3;
7446 id->ieee[1] = 0x02;
7447 id->ieee[2] = 0x00;
7448 } else {

--- 50 unchanged lines hidden (view full) ---

7499 nvme_init_subnqn(n);
7500
7501 id->psd[0].mp = cpu_to_le16(0x9c4);
7502 id->psd[0].enlat = cpu_to_le32(0x10);
7503 id->psd[0].exlat = cpu_to_le32(0x4);
7504
7505 if (n->subsys) {
7506 id->cmic |= NVME_CMIC_MULTI_CTRL;
7507 ctratt |= NVME_CTRATT_ENDGRPS;
7508
7509 id->endgidmax = cpu_to_le16(0x1);
7462 }
7463
7510 }
7511
7512 id->ctratt = cpu_to_le32(ctratt);
7513
7464 NVME_CAP_SET_MQES(cap, 0x7ff);
7465 NVME_CAP_SET_CQR(cap, 1);
7466 NVME_CAP_SET_TO(cap, 0xf);
7467 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NVM);
7468 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_CSI_SUPP);
7469 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_ADMIN_ONLY);
7470 NVME_CAP_SET_MPSMAX(cap, 4);
7471 NVME_CAP_SET_CMBS(cap, n->params.cmb_size_mb ? 1 : 0);

--- 301 unchanged lines hidden --- 		7514 NVME_CAP_SET_MQES(cap, 0x7ff);
7515 NVME_CAP_SET_CQR(cap, 1);
7516 NVME_CAP_SET_TO(cap, 0xf);
7517 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NVM);
7518 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_CSI_SUPP);
7519 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_ADMIN_ONLY);
7520 NVME_CAP_SET_MPSMAX(cap, 4);
7521 NVME_CAP_SET_CMBS(cap, n->params.cmb_size_mb ? 1 : 0);

--- 301 unchanged lines hidden ---