vmxnet3.c (52dd5f6f70276518dd21cd3a72cb95495df33bc9) vmxnet3.c (a51db5802744b274ab40385dd9fe8354722fcc4d)
1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:

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646 }
647
648 vmxnet3_dump_tx_descr(&txd);
649
650 if (!s->skip_current_tx_pkt) {
651 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
652 data_pa = txd.addr;
653
1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:

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646 }
647
648 vmxnet3_dump_tx_descr(&txd);
649
650 if (!s->skip_current_tx_pkt) {
651 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
652 data_pa = txd.addr;
653
654 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt,
655 data_pa,
656 data_len)) {
654 if (!net_tx_pkt_add_raw_fragment_pci(s->tx_pkt, PCI_DEVICE(s),
655 data_pa, data_len)) {
657 s->skip_current_tx_pkt = true;
658 }
659 }
660
661 if (s->tx_sop) {
662 vmxnet3_tx_retrieve_metadata(s, &txd);
663 s->tx_sop = false;
664 }

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673 } else {
674 vmxnet3_on_tx_done_update_stats(s, qidx,
675 VMXNET3_PKT_STATUS_ERROR);
676 }
677
678 vmxnet3_complete_packet(s, qidx, txd_idx);
679 s->tx_sop = true;
680 s->skip_current_tx_pkt = false;
656 s->skip_current_tx_pkt = true;
657 }
658 }
659
660 if (s->tx_sop) {
661 vmxnet3_tx_retrieve_metadata(s, &txd);
662 s->tx_sop = false;
663 }

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672 } else {
673 vmxnet3_on_tx_done_update_stats(s, qidx,
674 VMXNET3_PKT_STATUS_ERROR);
675 }
676
677 vmxnet3_complete_packet(s, qidx, txd_idx);
678 s->tx_sop = true;
679 s->skip_current_tx_pkt = false;
681 net_tx_pkt_reset(s->tx_pkt, PCI_DEVICE(s));
680 net_tx_pkt_reset(s->tx_pkt,
681 net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
682 }
683 }
684}
685
686static inline void
687vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
689{

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1154 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1155 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
1156}
1157
1158static void vmxnet3_deactivate_device(VMXNET3State *s)
1159{
1160 if (s->device_active) {
1161 VMW_CBPRN("Deactivating vmxnet3...");
682 }
683 }
684}
685
686static inline void
687vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
689{

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1154 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1155 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
1156}
1157
1158static void vmxnet3_deactivate_device(VMXNET3State *s)
1159{
1160 if (s->device_active) {
1161 VMW_CBPRN("Deactivating vmxnet3...");
1162 net_tx_pkt_reset(s->tx_pkt, PCI_DEVICE(s));
1162 net_tx_pkt_reset(s->tx_pkt, net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
1163 net_tx_pkt_uninit(s->tx_pkt);
1164 net_rx_pkt_uninit(s->rx_pkt);
1165 s->device_active = false;
1166 }
1167}
1168
1169static void vmxnet3_reset(VMXNET3State *s)
1170{

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1514 /* Fill device-managed parameters for queues */
1515 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
1516 ctrl.txThreshold,
1517 VMXNET3_DEF_TX_THRESHOLD);
1518 }
1519
1520 /* Preallocate TX packet wrapper */
1521 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1163 net_tx_pkt_uninit(s->tx_pkt);
1164 net_rx_pkt_uninit(s->rx_pkt);
1165 s->device_active = false;
1166 }
1167}
1168
1169static void vmxnet3_reset(VMXNET3State *s)
1170{

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1514 /* Fill device-managed parameters for queues */
1515 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
1516 ctrl.txThreshold,
1517 VMXNET3_DEF_TX_THRESHOLD);
1518 }
1519
1520 /* Preallocate TX packet wrapper */
1521 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1522 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags);
1522 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
1523 net_rx_pkt_init(&s->rx_pkt);
1524
1525 /* Read rings memory locations for RX queues */
1526 for (i = 0; i < s->rxq_num; i++) {
1527 int j;
1528 hwaddr qd_pa =
1529 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1530 i * sizeof(struct Vmxnet3_RxQueueDesc);

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2394 VMSTATE_END_OF_LIST()
2395 }
2396};
2397
2398static int vmxnet3_post_load(void *opaque, int version_id)
2399{
2400 VMXNET3State *s = opaque;
2401
1523 net_rx_pkt_init(&s->rx_pkt);
1524
1525 /* Read rings memory locations for RX queues */
1526 for (i = 0; i < s->rxq_num; i++) {
1527 int j;
1528 hwaddr qd_pa =
1529 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1530 i * sizeof(struct Vmxnet3_RxQueueDesc);

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2394 VMSTATE_END_OF_LIST()
2395 }
2396};
2397
2398static int vmxnet3_post_load(void *opaque, int version_id)
2399{
2400 VMXNET3State *s = opaque;
2401
2402 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags);
2402 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
2403 net_rx_pkt_init(&s->rx_pkt);
2404
2405 if (s->msix_used) {
2406 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2407 }
2408
2409 if (!vmxnet3_validate_queues(s)) {
2410 return -1;

--- 132 unchanged lines hidden --- 		2403 net_rx_pkt_init(&s->rx_pkt);
2404
2405 if (s->msix_used) {
2406 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2407 }
2408
2409 if (!vmxnet3_validate_queues(s)) {
2410 return -1;

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