rx_icu.c (d88d5a3806d78dcfca648c62dae9d88d3e803bd2) rx_icu.c (d73415a315471ac0b127ed3fad45c8ec5d711de1)
1/*
2 * RX Interrupt Control Unit
3 *
4 * Warning: Only ICUa is supported.
5 *
6 * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
7 * (Rev.1.40 R01UH0033EJ0140)
8 *

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76 return (icu->ipr[icu->map[n]] << 8) | n;
77}
78
79static void rxicu_request(RXICUState *icu, int n_IRQ)
80{
81 int enable;
82
83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
1/*
2 * RX Interrupt Control Unit
3 *
4 * Warning: Only ICUa is supported.
5 *
6 * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
7 * (Rev.1.40 R01UH0033EJ0140)
8 *

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76 return (icu->ipr[icu->map[n]] << 8) | n;
77}
78
79static void rxicu_request(RXICUState *icu, int n_IRQ)
80{
81 int enable;
82
83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
84 if (n_IRQ > 0 && enable != 0 && atomic_read(&icu->req_irq) < 0) {
85 atomic_set(&icu->req_irq, n_IRQ);
84 if (n_IRQ > 0 && enable != 0 && qatomic_read(&icu->req_irq) < 0) {
85 qatomic_set(&icu->req_irq, n_IRQ);
86 set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ));
87 }
88}
89
90static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
91{
92 RXICUState *icu = opaque;
93 struct IRQSource *src;

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119 issue = ((level ^ src->level) & 1);
120 src->level = level;
121 break;
122 default:
123 g_assert_not_reached();
124 }
125 if (issue == 0 && src->sense == TRG_LEVEL) {
126 icu->ir[n_IRQ] = 0;
86 set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ));
87 }
88}
89
90static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
91{
92 RXICUState *icu = opaque;
93 struct IRQSource *src;

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119 issue = ((level ^ src->level) & 1);
120 src->level = level;
121 break;
122 default:
123 g_assert_not_reached();
124 }
125 if (issue == 0 && src->sense == TRG_LEVEL) {
126 icu->ir[n_IRQ] = 0;
127 if (atomic_read(&icu->req_irq) == n_IRQ) {
127 if (qatomic_read(&icu->req_irq) == n_IRQ) {
128 /* clear request */
129 set_irq(icu, n_IRQ, 0);
128 /* clear request */
129 set_irq(icu, n_IRQ, 0);
130 atomic_set(&icu->req_irq, -1);
130 qatomic_set(&icu->req_irq, -1);
131 }
132 return;
133 }
134 if (issue) {
135 icu->ir[n_IRQ] = 1;
136 rxicu_request(icu, n_IRQ);
137 }
138}
139
140static void rxicu_ack_irq(void *opaque, int no, int level)
141{
142 RXICUState *icu = opaque;
143 int i;
144 int n_IRQ;
145 int max_pri;
146
131 }
132 return;
133 }
134 if (issue) {
135 icu->ir[n_IRQ] = 1;
136 rxicu_request(icu, n_IRQ);
137 }
138}
139
140static void rxicu_ack_irq(void *opaque, int no, int level)
141{
142 RXICUState *icu = opaque;
143 int i;
144 int n_IRQ;
145 int max_pri;
146
147 n_IRQ = atomic_read(&icu->req_irq);
147 n_IRQ = qatomic_read(&icu->req_irq);
148 if (n_IRQ < 0) {
149 return;
150 }
148 if (n_IRQ < 0) {
149 return;
150 }
151 atomic_set(&icu->req_irq, -1);
151 qatomic_set(&icu->req_irq, -1);
152 if (icu->src[n_IRQ].sense != TRG_LEVEL) {
153 icu->ir[n_IRQ] = 0;
154 }
155
156 max_pri = 0;
157 n_IRQ = -1;
158 for (i = 0; i < NR_IRQS; i++) {
159 if (icu->ir[i]) {

--- 238 unchanged lines hidden --- 		152 if (icu->src[n_IRQ].sense != TRG_LEVEL) {
153 icu->ir[n_IRQ] = 0;
154 }
155
156 max_pri = 0;
157 n_IRQ = -1;
158 for (i = 0; i < NR_IRQS; i++) {
159 if (icu->ir[i]) {

--- 238 unchanged lines hidden ---