riscv_aclint.c (0cac736e73723850a99e5142e35d14d8f8efb232) riscv_aclint.c (9323e79f10e5f5d8fffc3b307776173ca11faeae)
1/*
2 * RISC-V ACLINT (Advanced Core Local Interruptor)
3 * URL: https://github.com/riscv/riscv-aclint
4 *
5 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * Copyright (c) 2017 SiFive, Inc.
7 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
8 *

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458 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
459
460 swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
461 qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
462
463 /* Claim software interrupt bits */
464 for (i = 0; i < swi->num_harts; i++) {
465 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
1/*
2 * RISC-V ACLINT (Advanced Core Local Interruptor)
3 * URL: https://github.com/riscv/riscv-aclint
4 *
5 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * Copyright (c) 2017 SiFive, Inc.
7 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
8 *

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458 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
459
460 swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
461 qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
462
463 /* Claim software interrupt bits */
464 for (i = 0; i < swi->num_harts; i++) {
465 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
466 /* We don't claim mip.SSIP because it is writeable by software */
466 /* We don't claim mip.SSIP because it is writable by software */
467 if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
468 error_report("MSIP already claimed");
469 exit(1);
470 }
471 }
472}
473
474static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)

--- 71 unchanged lines hidden --- 		467 if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
468 error_report("MSIP already claimed");
469 exit(1);
470 }
471 }
472}
473
474static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)

--- 71 unchanged lines hidden ---