pnv_xive2.c (cce84fc9193e2566b4f7f9de5a13e7ed360d44d9) pnv_xive2.c (32af01f83a763ccbba39c1cbc424e1b724d233df)
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

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950 /*
951 * ESB cache updates (not modeled)
952 */
953 case VC_ESBC_FLUSH_CTRL:
954 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID;
955 val = xive->vc_regs[reg];
956 break;
957
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

--- 941 unchanged lines hidden (view full) ---

950 /*
951 * ESB cache updates (not modeled)
952 */
953 case VC_ESBC_FLUSH_CTRL:
954 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID;
955 val = xive->vc_regs[reg];
956 break;
957
958 case VC_ESBC_CFG:
959 val = xive->vc_regs[reg];
960 break;
961
958 /*
959 * EAS cache updates (not modeled)
960 */
961 case VC_EASC_FLUSH_CTRL:
962 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID;
963 val = xive->vc_regs[reg];
964 break;
965

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1041 * ESB cache updates (not modeled)
1042 */
1043 /* case VC_ESBC_FLUSH_CTRL: */
1044 case VC_ESBC_FLUSH_POLL:
1045 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID;
1046 /* ESB update */
1047 break;
1048
962 /*
963 * EAS cache updates (not modeled)
964 */
965 case VC_EASC_FLUSH_CTRL:
966 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID;
967 val = xive->vc_regs[reg];
968 break;
969

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1045 * ESB cache updates (not modeled)
1046 */
1047 /* case VC_ESBC_FLUSH_CTRL: */
1048 case VC_ESBC_FLUSH_POLL:
1049 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID;
1050 /* ESB update */
1051 break;
1052
1053 case VC_ESBC_CFG:
1054 break;
1055
1049 /*
1050 * EAS cache updates (not modeled)
1051 */
1052 /* case VC_EASC_FLUSH_CTRL: */
1053 case VC_EASC_FLUSH_POLL:
1054 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID;
1055 /* EAS update */
1056 break;

--- 1066 unchanged lines hidden --- 		1056 /*
1057 * EAS cache updates (not modeled)
1058 */
1059 /* case VC_EASC_FLUSH_CTRL: */
1060 case VC_EASC_FLUSH_POLL:
1061 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID;
1062 /* EAS update */
1063 break;

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