pnv_xive2.c (707ea7ab4d55e0d907f72280eb2e4d376efeddf7) pnv_xive2.c (95d729e2bc5b46d40e71971043e03d9cc9503e9a)
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

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1606 .max_access_size = 8,
1607 },
1608};
1609
1610/*
1611 * TIMA ops
1612 */
1613
1/*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */

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1606 .max_access_size = 8,
1607 },
1608};
1609
1610/*
1611 * TIMA ops
1612 */
1613
1614/*
1615 * Special TIMA offsets to handle accesses in a POWER10 way.
1616 *
1617 * Only the CAM line updates done by the hypervisor should be handled
1618 * specifically.
1619 */
1620#define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT)
1621#define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2))
1622#define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX)
1623
1614static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
1615 uint64_t value, unsigned size)
1616{
1617 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1618 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1619 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1624static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
1625 uint64_t value, unsigned size)
1626{
1627 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1628 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1629 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1630 XivePresenter *xptr = XIVE_PRESENTER(xive);
1620
1631
1632 /* TODO: should we switch the TM ops table instead ? */
1633 if (offset == HV_PUSH_OS_CTX_OFFSET) {
1634 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);
1635 return;
1636 }
1637
1621 /* Other TM ops are the same as XIVE1 */
1638 /* Other TM ops are the same as XIVE1 */
1622 xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
1639 xive_tctx_tm_write(xptr, tctx, offset, value, size);
1623}
1624
1625static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
1626{
1627 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1628 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1629 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1640}
1641
1642static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
1643{
1644 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1645 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1646 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1647 XivePresenter *xptr = XIVE_PRESENTER(xive);
1630
1648
1649 /* TODO: should we switch the TM ops table instead ? */
1650 if (offset == HV_PULL_OS_CTX_OFFSET) {
1651 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);
1652 }
1653
1631 /* Other TM ops are the same as XIVE1 */
1654 /* Other TM ops are the same as XIVE1 */
1632 return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
1655 return xive_tctx_tm_read(xptr, tctx, offset, size);
1633}
1634
1635static const MemoryRegionOps pnv_xive2_tm_ops = {
1636 .read = pnv_xive2_tm_read,
1637 .write = pnv_xive2_tm_write,
1638 .endianness = DEVICE_BIG_ENDIAN,
1639 .valid = {
1640 .min_access_size = 1,

--- 419 unchanged lines hidden --- 		1656}
1657
1658static const MemoryRegionOps pnv_xive2_tm_ops = {
1659 .read = pnv_xive2_tm_read,
1660 .write = pnv_xive2_tm_write,
1661 .endianness = DEVICE_BIG_ENDIAN,
1662 .valid = {
1663 .min_access_size = 1,

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