bcm2836_control.c (98c710f2d5cdf37f29a267352eb1f3c28cbf369d) bcm2836_control.c (67d80321f26d9ea2b623ffac567a2f758ceae037)
1/*
2 * Rasperry Pi 2 emulation ARM control logic module.
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 *
6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
7 * This code is licensed under the GNU GPLv2 and later.
8 *
9 * At present, only implements interrupt routing, and mailboxes (i.e.,
1/*
2 * Rasperry Pi 2 emulation ARM control logic module.
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 *
6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
7 * This code is licensed under the GNU GPLv2 and later.
8 *
9 * At present, only implements interrupt routing, and mailboxes (i.e.,
10 * not local timer, PMU interrupt, or AXI counters).
10 * not PMU interrupt, or AXI counters).
11 *
11 *
12 * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
13 *
12 * Ref:
13 * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
14 */
15
16#include "qemu/osdep.h"
17#include "hw/intc/bcm2836_control.h"
18#include "qemu/log.h"
19
20#define REG_GPU_ROUTE 0x0c
14 * Ref:
15 * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
16 */
17
18#include "qemu/osdep.h"
19#include "hw/intc/bcm2836_control.h"
20#include "qemu/log.h"
21
22#define REG_GPU_ROUTE 0x0c
23#define REG_LOCALTIMERROUTING 0x24
24#define REG_LOCALTIMERCONTROL 0x34
25#define REG_LOCALTIMERACK 0x38
21#define REG_TIMERCONTROL 0x40
22#define REG_MBOXCONTROL 0x50
23#define REG_IRQSRC 0x60
24#define REG_FIQSRC 0x70
25#define REG_MBOX0_WR 0x80
26#define REG_MBOX0_RDCLR 0xc0
27#define REG_LIMIT 0x100
28

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38#define IRQ_MAILBOX2 6
39#define IRQ_MAILBOX3 7
40#define IRQ_GPU 8
41#define IRQ_PMU 9
42#define IRQ_AXI 10
43#define IRQ_TIMER 11
44#define IRQ_MAX IRQ_TIMER
45
26#define REG_TIMERCONTROL 0x40
27#define REG_MBOXCONTROL 0x50
28#define REG_IRQSRC 0x60
29#define REG_FIQSRC 0x70
30#define REG_MBOX0_WR 0x80
31#define REG_MBOX0_RDCLR 0xc0
32#define REG_LIMIT 0x100
33

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43#define IRQ_MAILBOX2 6
44#define IRQ_MAILBOX3 7
45#define IRQ_GPU 8
46#define IRQ_PMU 9
47#define IRQ_AXI 10
48#define IRQ_TIMER 11
49#define IRQ_MAX IRQ_TIMER
50
51#define LOCALTIMER_FREQ 38400000
52#define LOCALTIMER_INTFLAG (1 << 31)
53#define LOCALTIMER_RELOAD (1 << 30)
54#define LOCALTIMER_INTENABLE (1 << 29)
55#define LOCALTIMER_ENABLE (1 << 28)
56#define LOCALTIMER_VALUE(x) ((x) & 0xfffffff)
57
46static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
47 uint32_t controlreg, uint8_t controlidx)
48{
49 if (FIQ_BIT(controlreg, controlidx)) {
50 /* deliver a FIQ */
51 s->fiqsrc[core] |= (uint32_t)1 << irq;
52 } else if (IRQ_BIT(controlreg, controlidx)) {
53 /* deliver an IRQ */

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73 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU;
74 }
75
76 if (s->gpu_fiq) {
77 assert(s->route_gpu_fiq < BCM2836_NCORES);
78 s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
79 }
80
58static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
59 uint32_t controlreg, uint8_t controlidx)
60{
61 if (FIQ_BIT(controlreg, controlidx)) {
62 /* deliver a FIQ */
63 s->fiqsrc[core] |= (uint32_t)1 << irq;
64 } else if (IRQ_BIT(controlreg, controlidx)) {
65 /* deliver an IRQ */

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85 s->irqsrc[s->route_gpu_irq] |= (uint32_t)1 << IRQ_GPU;
86 }
87
88 if (s->gpu_fiq) {
89 assert(s->route_gpu_fiq < BCM2836_NCORES);
90 s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
91 }
92
93 /*
94 * handle the control module 'local timer' interrupt for one of the
95 * cores' IRQ/FIQ; this is distinct from the per-CPU timer
96 * interrupts handled below.
97 */
98 if ((s->local_timer_control & LOCALTIMER_INTENABLE) &&
99 (s->local_timer_control & LOCALTIMER_INTFLAG)) {
100 if (s->route_localtimer & 4) {
101 s->fiqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
102 } else {
103 s->irqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
104 }
105 }
106
81 for (i = 0; i < BCM2836_NCORES; i++) {
82 /* handle local timer interrupts for this core */
83 if (s->timerirqs[i]) {
84 assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */
85 for (j = 0; j <= IRQ_CNTVIRQ; j++) {
86 if ((s->timerirqs[i] & (1 << j)) != 0) {
87 /* local interrupt j is set */
88 deliver_local(s, i, j, s->timercontrol[i], j);

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157{
158 BCM2836ControlState *s = opaque;
159
160 s->gpu_fiq = level;
161
162 bcm2836_control_update(s);
163}
164
107 for (i = 0; i < BCM2836_NCORES; i++) {
108 /* handle local timer interrupts for this core */
109 if (s->timerirqs[i]) {
110 assert(s->timerirqs[i] < (1 << (IRQ_CNTVIRQ + 1))); /* sane mask? */
111 for (j = 0; j <= IRQ_CNTVIRQ; j++) {
112 if ((s->timerirqs[i] & (1 << j)) != 0) {
113 /* local interrupt j is set */
114 deliver_local(s, i, j, s->timercontrol[i], j);

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183{
184 BCM2836ControlState *s = opaque;
185
186 s->gpu_fiq = level;
187
188 bcm2836_control_update(s);
189}
190
191static void bcm2836_control_local_timer_set_next(void *opaque)
192{
193 BCM2836ControlState *s = opaque;
194 uint64_t next_event;
195
196 assert(LOCALTIMER_VALUE(s->local_timer_control) > 0);
197
198 next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
199 muldiv64(LOCALTIMER_VALUE(s->local_timer_control),
200 NANOSECONDS_PER_SECOND, LOCALTIMER_FREQ);
201 timer_mod(&s->timer, next_event);
202}
203
204static void bcm2836_control_local_timer_tick(void *opaque)
205{
206 BCM2836ControlState *s = opaque;
207
208 bcm2836_control_local_timer_set_next(s);
209
210 s->local_timer_control |= LOCALTIMER_INTFLAG;
211 bcm2836_control_update(s);
212}
213
214static void bcm2836_control_local_timer_control(void *opaque, uint32_t val)
215{
216 BCM2836ControlState *s = opaque;
217
218 s->local_timer_control = val;
219 if (val & LOCALTIMER_ENABLE) {
220 bcm2836_control_local_timer_set_next(s);
221 } else {
222 timer_del(&s->timer);
223 }
224}
225
226static void bcm2836_control_local_timer_ack(void *opaque, uint32_t val)
227{
228 BCM2836ControlState *s = opaque;
229
230 if (val & LOCALTIMER_INTFLAG) {
231 s->local_timer_control &= ~LOCALTIMER_INTFLAG;
232 }
233 if ((val & LOCALTIMER_RELOAD) &&
234 (s->local_timer_control & LOCALTIMER_ENABLE)) {
235 bcm2836_control_local_timer_set_next(s);
236 }
237}
238
165static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
166{
167 BCM2836ControlState *s = opaque;
168
169 if (offset == REG_GPU_ROUTE) {
170 assert(s->route_gpu_fiq < BCM2836_NCORES
171 && s->route_gpu_irq < BCM2836_NCORES);
172 return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
239static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
240{
241 BCM2836ControlState *s = opaque;
242
243 if (offset == REG_GPU_ROUTE) {
244 assert(s->route_gpu_fiq < BCM2836_NCORES
245 && s->route_gpu_irq < BCM2836_NCORES);
246 return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
247 } else if (offset == REG_LOCALTIMERROUTING) {
248 return s->route_localtimer;
249 } else if (offset == REG_LOCALTIMERCONTROL) {
250 return s->local_timer_control;
251 } else if (offset == REG_LOCALTIMERACK) {
252 return 0;
173 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
174 return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
175 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
176 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
177 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
178 return s->irqsrc[(offset - REG_IRQSRC) >> 2];
179 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
180 return s->fiqsrc[(offset - REG_FIQSRC) >> 2];

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190static void bcm2836_control_write(void *opaque, hwaddr offset,
191 uint64_t val, unsigned size)
192{
193 BCM2836ControlState *s = opaque;
194
195 if (offset == REG_GPU_ROUTE) {
196 s->route_gpu_irq = val & 0x3;
197 s->route_gpu_fiq = (val >> 2) & 0x3;
253 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
254 return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
255 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
256 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
257 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
258 return s->irqsrc[(offset - REG_IRQSRC) >> 2];
259 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
260 return s->fiqsrc[(offset - REG_FIQSRC) >> 2];

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270static void bcm2836_control_write(void *opaque, hwaddr offset,
271 uint64_t val, unsigned size)
272{
273 BCM2836ControlState *s = opaque;
274
275 if (offset == REG_GPU_ROUTE) {
276 s->route_gpu_irq = val & 0x3;
277 s->route_gpu_fiq = (val >> 2) & 0x3;
278 } else if (offset == REG_LOCALTIMERROUTING) {
279 s->route_localtimer = val & 7;
280 } else if (offset == REG_LOCALTIMERCONTROL) {
281 bcm2836_control_local_timer_control(s, val);
282 } else if (offset == REG_LOCALTIMERACK) {
283 bcm2836_control_local_timer_ack(s, val);
198 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
199 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
200 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
201 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
202 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
203 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
204 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
205 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;

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222
223static void bcm2836_control_reset(DeviceState *d)
224{
225 BCM2836ControlState *s = BCM2836_CONTROL(d);
226 int i;
227
228 s->route_gpu_irq = s->route_gpu_fiq = 0;
229
284 } else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
285 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
286 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
287 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
288 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
289 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
290 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
291 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;

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308
309static void bcm2836_control_reset(DeviceState *d)
310{
311 BCM2836ControlState *s = BCM2836_CONTROL(d);
312 int i;
313
314 s->route_gpu_irq = s->route_gpu_fiq = 0;
315
316 timer_del(&s->timer);
317 s->route_localtimer = 0;
318 s->local_timer_control = 0;
319
230 for (i = 0; i < BCM2836_NCORES; i++) {
231 s->timercontrol[i] = 0;
232 s->mailboxcontrol[i] = 0;
233 }
234
235 for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) {
236 s->mailboxes[i] = 0;
237 }

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258
259 /* IRQ and FIQ inputs from upstream bcm2835 controller */
260 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1);
261 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1);
262
263 /* outputs to CPU cores */
264 qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
265 qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
320 for (i = 0; i < BCM2836_NCORES; i++) {
321 s->timercontrol[i] = 0;
322 s->mailboxcontrol[i] = 0;
323 }
324
325 for (i = 0; i < BCM2836_NCORES * BCM2836_MBPERCORE; i++) {
326 s->mailboxes[i] = 0;
327 }

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348
349 /* IRQ and FIQ inputs from upstream bcm2835 controller */
350 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_irq, "gpu-irq", 1);
351 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1);
352
353 /* outputs to CPU cores */
354 qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
355 qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
356
357 /* create a qemu virtual timer */
358 timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL,
359 bcm2836_control_local_timer_tick, s);
266}
267
268static const VMStateDescription vmstate_bcm2836_control = {
269 .name = TYPE_BCM2836_CONTROL,
360}
361
362static const VMStateDescription vmstate_bcm2836_control = {
363 .name = TYPE_BCM2836_CONTROL,
270 .version_id = 1,
364 .version_id = 2,
271 .minimum_version_id = 1,
272 .fields = (VMStateField[]) {
273 VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
274 BCM2836_NCORES * BCM2836_MBPERCORE),
275 VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState),
276 VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState),
277 VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
278 VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
279 BCM2836_NCORES),
365 .minimum_version_id = 1,
366 .fields = (VMStateField[]) {
367 VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
368 BCM2836_NCORES * BCM2836_MBPERCORE),
369 VMSTATE_UINT8(route_gpu_irq, BCM2836ControlState),
370 VMSTATE_UINT8(route_gpu_fiq, BCM2836ControlState),
371 VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
372 VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
373 BCM2836_NCORES),
374 VMSTATE_TIMER_V(timer, BCM2836ControlState, 2),
375 VMSTATE_UINT32_V(local_timer_control, BCM2836ControlState, 2),
376 VMSTATE_UINT8_V(route_localtimer, BCM2836ControlState, 2),
280 VMSTATE_END_OF_LIST()
281 }
282};
283
284static void bcm2836_control_class_init(ObjectClass *klass, void *data)
285{
286 DeviceClass *dc = DEVICE_CLASS(klass);
287

--- 18 unchanged lines hidden --- 		377 VMSTATE_END_OF_LIST()
378 }
379};
380
381static void bcm2836_control_class_init(ObjectClass *klass, void *data)
382{
383 DeviceClass *dc = DEVICE_CLASS(klass);
384

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