bcm2836_control.c (95a9457fd44ad97c518858a4e1586a5498f9773c) bcm2836_control.c (e1ecf8c8026fc1b1a742160e69c0ab3087bc2841)
1/*
2 * Rasperry Pi 2 emulation ARM control logic module.
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 *
6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
7 * This code is licensed under the GNU GPLv2 and later.
8 *

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259 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
260 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
261 return s->irqsrc[(offset - REG_IRQSRC) >> 2];
262 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
263 return s->fiqsrc[(offset - REG_FIQSRC) >> 2];
264 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
265 return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2];
266 } else {
1/*
2 * Rasperry Pi 2 emulation ARM control logic module.
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 *
6 * Based on bcm2835_ic.c (Raspberry Pi emulation) (c) 2012 Gregory Estrade
7 * This code is licensed under the GNU GPLv2 and later.
8 *

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259 return s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2];
260 } else if (offset >= REG_IRQSRC && offset < REG_FIQSRC) {
261 return s->irqsrc[(offset - REG_IRQSRC) >> 2];
262 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) {
263 return s->fiqsrc[(offset - REG_FIQSRC) >> 2];
264 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
265 return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2];
266 } else {
267 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
267 qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
268 __func__, offset);
269 return 0;
270 }
271}
272
273static void bcm2836_control_write(void *opaque, hwaddr offset,
274 uint64_t val, unsigned size)
275{

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288 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
289 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
290 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
291 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
292 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
293 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
294 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;
295 } else {
268 __func__, offset);
269 return 0;
270 }
271}
272
273static void bcm2836_control_write(void *opaque, hwaddr offset,
274 uint64_t val, unsigned size)
275{

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288 s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
289 } else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
290 s->mailboxcontrol[(offset - REG_MBOXCONTROL) >> 2] = val & 0xff;
291 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) {
292 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val;
293 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) {
294 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val;
295 } else {
296 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
297 __func__, offset);
296 qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
297 " value 0x%"PRIx64"\n",
298 __func__, offset, val);
298 return;
299 }
300
301 bcm2836_control_update(s);
302}
303
304static const MemoryRegionOps bcm2836_control_ops = {
305 .read = bcm2836_control_read,

--- 100 unchanged lines hidden --- 		299 return;
300 }
301
302 bcm2836_control_update(s);
303}
304
305static const MemoryRegionOps bcm2836_control_ops = {
306 .read = bcm2836_control_read,

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