armv7m_nvic.c (9ac5df20f51fabcba0d902025df4bd7ea987c158) armv7m_nvic.c (7fbc6a403a0aab834e764fa61d81ed8586cfe352)
1/*
2 * ARM Nested Vectored Interrupt Controller
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 *

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1257 case 0xd80: /* CSSIDR */
1258 {
1259 int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK;
1260 return cpu->ccsidr[idx];
1261 }
1262 case 0xd84: /* CSSELR */
1263 return cpu->env.v7m.csselr[attrs.secure];
1264 case 0xd88: /* CPACR */
1/*
2 * ARM Nested Vectored Interrupt Controller
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 *

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1257 case 0xd80: /* CSSIDR */
1258 {
1259 int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK;
1260 return cpu->ccsidr[idx];
1261 }
1262 case 0xd84: /* CSSELR */
1263 return cpu->env.v7m.csselr[attrs.secure];
1264 case 0xd88: /* CPACR */
1265 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1265 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
1266 return 0;
1267 }
1268 return cpu->env.v7m.cpacr[attrs.secure];
1269 case 0xd8c: /* NSACR */
1266 return 0;
1267 }
1268 return cpu->env.v7m.cpacr[attrs.secure];
1269 case 0xd8c: /* NSACR */
1270 if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1270 if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
1271 return 0;
1272 }
1273 return cpu->env.v7m.nsacr;
1274 /* TODO: Implement debug registers. */
1275 case 0xd90: /* MPU_TYPE */
1276 /* Unified MPU; if the MPU is not present this value is zero */
1277 return cpu->pmsav7_dregion << 8;
1278 break;

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1412 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1413 goto bad_offset;
1414 }
1415 if (!attrs.secure) {
1416 return 0;
1417 }
1418 return cpu->env.v7m.sfar;
1419 case 0xf34: /* FPCCR */
1271 return 0;
1272 }
1273 return cpu->env.v7m.nsacr;
1274 /* TODO: Implement debug registers. */
1275 case 0xd90: /* MPU_TYPE */
1276 /* Unified MPU; if the MPU is not present this value is zero */
1277 return cpu->pmsav7_dregion << 8;
1278 break;

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1412 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1413 goto bad_offset;
1414 }
1415 if (!attrs.secure) {
1416 return 0;
1417 }
1418 return cpu->env.v7m.sfar;
1419 case 0xf34: /* FPCCR */
1420 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1420 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
1421 return 0;
1422 }
1423 if (attrs.secure) {
1424 return cpu->env.v7m.fpccr[M_REG_S];
1425 } else {
1426 /*
1427 * NS can read LSPEN, CLRONRET and MONRDY. It can read
1428 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0;

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1439 }
1440
1441 value &= mask;
1442
1443 value |= cpu->env.v7m.fpccr[M_REG_NS];
1444 return value;
1445 }
1446 case 0xf38: /* FPCAR */
1421 return 0;
1422 }
1423 if (attrs.secure) {
1424 return cpu->env.v7m.fpccr[M_REG_S];
1425 } else {
1426 /*
1427 * NS can read LSPEN, CLRONRET and MONRDY. It can read
1428 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0;

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1439 }
1440
1441 value &= mask;
1442
1443 value |= cpu->env.v7m.fpccr[M_REG_NS];
1444 return value;
1445 }
1446 case 0xf38: /* FPCAR */
1447 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1447 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
1448 return 0;
1449 }
1450 return cpu->env.v7m.fpcar[attrs.secure];
1451 case 0xf3c: /* FPDSCR */
1448 return 0;
1449 }
1450 return cpu->env.v7m.fpcar[attrs.secure];
1451 case 0xf3c: /* FPDSCR */
1452 if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1452 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
1453 return 0;
1454 }
1455 return cpu->env.v7m.fpdscr[attrs.secure];
1456 case 0xf40: /* MVFR0 */
1457 return cpu->isar.mvfr0;
1458 case 0xf44: /* MVFR1 */
1459 return cpu->isar.mvfr1;
1460 case 0xf48: /* MVFR2 */

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1706 "NVIC: Aux fault status registers unimplemented\n");
1707 break;
1708 case 0xd84: /* CSSELR */
1709 if (!arm_v7m_csselr_razwi(cpu)) {
1710 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK;
1711 }
1712 break;
1713 case 0xd88: /* CPACR */
1453 return 0;
1454 }
1455 return cpu->env.v7m.fpdscr[attrs.secure];
1456 case 0xf40: /* MVFR0 */
1457 return cpu->isar.mvfr0;
1458 case 0xf44: /* MVFR1 */
1459 return cpu->isar.mvfr1;
1460 case 0xf48: /* MVFR2 */

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1706 "NVIC: Aux fault status registers unimplemented\n");
1707 break;
1708 case 0xd84: /* CSSELR */
1709 if (!arm_v7m_csselr_razwi(cpu)) {
1710 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK;
1711 }
1712 break;
1713 case 0xd88: /* CPACR */
1714 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1714 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1715 /* We implement only the Floating Point extension's CP10/CP11 */
1716 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
1717 }
1718 break;
1719 case 0xd8c: /* NSACR */
1715 /* We implement only the Floating Point extension's CP10/CP11 */
1716 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
1717 }
1718 break;
1719 case 0xd8c: /* NSACR */
1720 if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1720 if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
1721 /* We implement only the Floating Point extension's CP10/CP11 */
1722 cpu->env.v7m.nsacr = value & (3 << 10);
1723 }
1724 break;
1725 case 0xd90: /* MPU_TYPE */
1726 return; /* RO */
1727 case 0xd94: /* MPU_CTRL */
1728 if ((value &

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1946 }
1947
1948 if (excnum < s->num_irq) {
1949 armv7m_nvic_set_pending(s, excnum, false);
1950 }
1951 break;
1952 }
1953 case 0xf34: /* FPCCR */
1721 /* We implement only the Floating Point extension's CP10/CP11 */
1722 cpu->env.v7m.nsacr = value & (3 << 10);
1723 }
1724 break;
1725 case 0xd90: /* MPU_TYPE */
1726 return; /* RO */
1727 case 0xd94: /* MPU_CTRL */
1728 if ((value &

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1946 }
1947
1948 if (excnum < s->num_irq) {
1949 armv7m_nvic_set_pending(s, excnum, false);
1950 }
1951 break;
1952 }
1953 case 0xf34: /* FPCCR */
1954 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1954 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1955 /* Not all bits here are banked. */
1956 uint32_t fpccr_s;
1957
1958 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1959 /* Don't allow setting of bits not present in v7M */
1960 value &= (R_V7M_FPCCR_LSPACT_MASK |
1961 R_V7M_FPCCR_USER_MASK |
1962 R_V7M_FPCCR_THREAD_MASK |

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2000 cpu->env.v7m.fpccr[M_REG_NS] = value;
2001 } else {
2002 fpccr_s = value;
2003 }
2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s;
2005 }
2006 break;
2007 case 0xf38: /* FPCAR */
1955 /* Not all bits here are banked. */
1956 uint32_t fpccr_s;
1957
1958 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1959 /* Don't allow setting of bits not present in v7M */
1960 value &= (R_V7M_FPCCR_LSPACT_MASK |
1961 R_V7M_FPCCR_USER_MASK |
1962 R_V7M_FPCCR_THREAD_MASK |

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2000 cpu->env.v7m.fpccr[M_REG_NS] = value;
2001 } else {
2002 fpccr_s = value;
2003 }
2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s;
2005 }
2006 break;
2007 case 0xf38: /* FPCAR */
2008 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
2008 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
2009 value &= ~7;
2010 cpu->env.v7m.fpcar[attrs.secure] = value;
2011 }
2012 break;
2013 case 0xf3c: /* FPDSCR */
2009 value &= ~7;
2010 cpu->env.v7m.fpcar[attrs.secure] = value;
2011 }
2012 break;
2013 case 0xf3c: /* FPDSCR */
2014 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
2014 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
2015 value &= 0x07c00000;
2016 cpu->env.v7m.fpdscr[attrs.secure] = value;
2017 }
2018 break;
2019 case 0xf50: /* ICIALLU */
2020 case 0xf58: /* ICIMVAU */
2021 case 0xf5c: /* DCIMVAC */
2022 case 0xf60: /* DCISW */

--- 749 unchanged lines hidden --- 		2015 value &= 0x07c00000;
2016 cpu->env.v7m.fpdscr[attrs.secure] = value;
2017 }
2018 break;
2019 case 0xf50: /* ICIALLU */
2020 case 0xf58: /* ICIMVAU */
2021 case 0xf5c: /* DCIMVAC */
2022 case 0xf60: /* DCISW */

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