intel_iommu.c (a58614391d52ef8240071c1db5db6aceaf66a3ea) intel_iommu.c (80de52ba87d44bf63157900b8dd5ccd5bd795fd4)
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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1178
1179 /* Clear the index of Fault Recording Register */
1180 s->next_frcd_reg = 0;
1181 /* Ok - report back to driver */
1182 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1183 }
1184}
1185
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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1178
1179 /* Clear the index of Fault Recording Register */
1180 s->next_frcd_reg = 0;
1181 /* Ok - report back to driver */
1182 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1183 }
1184}
1185
1186/* Handle Interrupt Remap Enable/Disable */
1187static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1188{
1189 VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
1190
1191 if (en) {
1192 s->intr_enabled = true;
1193 /* Ok - report back to driver */
1194 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1195 } else {
1196 s->intr_enabled = false;
1197 /* Ok - report back to driver */
1198 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1199 }
1200}
1201
1186/* Handle write to Global Command Register */
1187static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1188{
1189 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1190 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1191 uint32_t changed = status ^ val;
1192
1193 VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);

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1202 if (changed & VTD_GCMD_QIE) {
1203 /* Queued Invalidation Enable */
1204 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1205 }
1206 if (val & VTD_GCMD_SIRTP) {
1207 /* Set/update the interrupt remapping root-table pointer */
1208 vtd_handle_gcmd_sirtp(s);
1209 }
1202/* Handle write to Global Command Register */
1203static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1204{
1205 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1206 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1207 uint32_t changed = status ^ val;
1208
1209 VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);

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1218 if (changed & VTD_GCMD_QIE) {
1219 /* Queued Invalidation Enable */
1220 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1221 }
1222 if (val & VTD_GCMD_SIRTP) {
1223 /* Set/update the interrupt remapping root-table pointer */
1224 vtd_handle_gcmd_sirtp(s);
1225 }
1226 if (changed & VTD_GCMD_IRE) {
1227 /* Interrupt remap enable/disable */
1228 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1229 }
1210}
1211
1212/* Handle write to Context Command Register */
1213static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1214{
1215 uint64_t ret;
1216 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1217

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1231
1232/* Handle write to Context Command Register */
1233static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1234{
1235 uint64_t ret;
1236 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1237

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