intel_iommu.c (80748eb4fbc70f0a3ae423f2c01cb5a4584d803f) intel_iommu.c (d5fd978d918516b7bc4224de432c7ef93ec089a3)
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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3929 } else {
3930 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
3931 PCI_FUNC(vtd_as->devfn));
3932 }
3933
3934 return;
3935}
3936
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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3929 } else {
3930 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
3931 PCI_FUNC(vtd_as->devfn));
3932 }
3933
3934 return;
3935}
3936
3937/* Do the initialization. It will also be called when reset, so pay
3938 * attention when adding new initialization stuff.
3939 */
3940static void vtd_init(IntelIOMMUState *s)
3937static void vtd_cap_init(IntelIOMMUState *s)
3941{
3942 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3943
3938{
3939 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3940
3944 memset(s->csr, 0, DMAR_REG_SIZE);
3945 memset(s->wmask, 0, DMAR_REG_SIZE);
3946 memset(s->w1cmask, 0, DMAR_REG_SIZE);
3947 memset(s->womask, 0, DMAR_REG_SIZE);
3948
3949 s->root = 0;
3950 s->root_scalable = false;
3951 s->dmar_enabled = false;
3952 s->intr_enabled = false;
3953 s->iq_head = 0;
3954 s->iq_tail = 0;
3955 s->iq = 0;
3956 s->iq_size = 0;
3957 s->qi_enabled = false;
3958 s->iq_last_desc_type = VTD_INV_DESC_NONE;
3959 s->iq_dw = false;
3960 s->next_frcd_reg = 0;
3961 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
3962 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
3963 VTD_CAP_MGAW(s->aw_bits);
3964 if (s->dma_drain) {
3965 s->cap |= VTD_CAP_DRAIN;
3966 }
3967 if (s->dma_translation) {
3968 if (s->aw_bits >= VTD_HOST_AW_39BIT) {
3969 s->cap |= VTD_CAP_SAGAW_39bit;
3970 }
3971 if (s->aw_bits >= VTD_HOST_AW_48BIT) {
3972 s->cap |= VTD_CAP_SAGAW_48bit;
3973 }
3974 }
3975 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
3976
3941 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
3942 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
3943 VTD_CAP_MGAW(s->aw_bits);
3944 if (s->dma_drain) {
3945 s->cap |= VTD_CAP_DRAIN;
3946 }
3947 if (s->dma_translation) {
3948 if (s->aw_bits >= VTD_HOST_AW_39BIT) {
3949 s->cap |= VTD_CAP_SAGAW_39bit;
3950 }
3951 if (s->aw_bits >= VTD_HOST_AW_48BIT) {
3952 s->cap |= VTD_CAP_SAGAW_48bit;
3953 }
3954 }
3955 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
3956
3977 /*
3978 * Rsvd field masks for spte
3979 */
3980 vtd_spte_rsvd[0] = ~0ULL;
3981 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
3982 x86_iommu->dt_supported);
3983 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
3984 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
3985 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
3986
3987 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
3988 x86_iommu->dt_supported);
3989 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
3990 x86_iommu->dt_supported);
3991
3992 if (s->scalable_mode || s->snoop_control) {
3993 vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
3994 vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
3995 vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
3996 }
3997
3998 if (x86_iommu_ir_supported(x86_iommu)) {
3999 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
4000 if (s->intr_eim == ON_OFF_AUTO_ON) {
4001 s->ecap |= VTD_ECAP_EIM;
4002 }
4003 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
4004 }
4005

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4022
4023 if (s->snoop_control) {
4024 s->ecap |= VTD_ECAP_SC;
4025 }
4026
4027 if (s->pasid) {
4028 s->ecap |= VTD_ECAP_PASID;
4029 }
3957 if (x86_iommu_ir_supported(x86_iommu)) {
3958 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
3959 if (s->intr_eim == ON_OFF_AUTO_ON) {
3960 s->ecap |= VTD_ECAP_EIM;
3961 }
3962 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
3963 }
3964

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3981
3982 if (s->snoop_control) {
3983 s->ecap |= VTD_ECAP_SC;
3984 }
3985
3986 if (s->pasid) {
3987 s->ecap |= VTD_ECAP_PASID;
3988 }
3989}
4030
3990
3991/*
3992 * Do the initialization. It will also be called when reset, so pay
3993 * attention when adding new initialization stuff.
3994 */
3995static void vtd_init(IntelIOMMUState *s)
3996{
3997 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3998
3999 memset(s->csr, 0, DMAR_REG_SIZE);
4000 memset(s->wmask, 0, DMAR_REG_SIZE);
4001 memset(s->w1cmask, 0, DMAR_REG_SIZE);
4002 memset(s->womask, 0, DMAR_REG_SIZE);
4003
4004 s->root = 0;
4005 s->root_scalable = false;
4006 s->dmar_enabled = false;
4007 s->intr_enabled = false;
4008 s->iq_head = 0;
4009 s->iq_tail = 0;
4010 s->iq = 0;
4011 s->iq_size = 0;
4012 s->qi_enabled = false;
4013 s->iq_last_desc_type = VTD_INV_DESC_NONE;
4014 s->iq_dw = false;
4015 s->next_frcd_reg = 0;
4016
4017 vtd_cap_init(s);
4018
4019 /*
4020 * Rsvd field masks for spte
4021 */
4022 vtd_spte_rsvd[0] = ~0ULL;
4023 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
4024 x86_iommu->dt_supported);
4025 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
4026 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
4027 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
4028
4029 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
4030 x86_iommu->dt_supported);
4031 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
4032 x86_iommu->dt_supported);
4033
4034 if (s->scalable_mode || s->snoop_control) {
4035 vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
4036 vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
4037 vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
4038 }
4039
4031 vtd_reset_caches(s);
4032
4033 /* Define registers with default values and bit semantics */
4034 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
4035 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
4036 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
4037 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
4038 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);

--- 244 unchanged lines hidden --- 		4040 vtd_reset_caches(s);
4041
4042 /* Define registers with default values and bit semantics */
4043 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
4044 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
4045 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
4046 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
4047 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);

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