intel_iommu.c (28ae3179fc52d2e4d870b635c4a412aab99759e7) intel_iommu.c (6ce12bd29777d41afef859652eaa62b5c964d3f7)
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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3367 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
3368 VTD_HOST_ADDRESS_WIDTH),
3369 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
3370 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
3371 DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
3372 DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
3373 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
3374 DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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3367 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
3368 VTD_HOST_ADDRESS_WIDTH),
3369 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
3370 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
3371 DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
3372 DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
3373 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
3374 DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
3375 DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),
3375 DEFINE_PROP_END_OF_LIST(),
3376};
3377
3378/* Read IRTE entry with specific index */
3379static bool vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
3380 VTD_IR_TableEntry *entry, uint16_t sid,
3381 bool do_fault)
3382{

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4133
4134 vtd_cap_init(s);
4135
4136 /*
4137 * Rsvd field masks for spte
4138 */
4139 vtd_spte_rsvd[0] = ~0ULL;
4140 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
3376 DEFINE_PROP_END_OF_LIST(),
3377};
3378
3379/* Read IRTE entry with specific index */
3380static bool vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
3381 VTD_IR_TableEntry *entry, uint16_t sid,
3382 bool do_fault)
3383{

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4134
4135 vtd_cap_init(s);
4136
4137 /*
4138 * Rsvd field masks for spte
4139 */
4140 vtd_spte_rsvd[0] = ~0ULL;
4141 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
4141 x86_iommu->dt_supported);
4142 x86_iommu->dt_supported && s->stale_tm);
4142 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
4143 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
4144 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
4145
4146 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
4143 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
4144 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
4145 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
4146
4147 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
4147 x86_iommu->dt_supported);
4148 x86_iommu->dt_supported && s->stale_tm);
4148 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
4149 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
4149 x86_iommu->dt_supported);
4150 x86_iommu->dt_supported && s->stale_tm);
4150
4151 if (s->scalable_mode || s->snoop_control) {
4152 vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
4153 vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
4154 vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
4155 }
4156
4157 vtd_reset_caches(s);

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4151
4152 if (s->scalable_mode || s->snoop_control) {
4153 vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
4154 vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
4155 vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
4156 }
4157
4158 vtd_reset_caches(s);

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