acpi-build.c (8612f8bd9fb667c62e9a56c67ab2e3af2798dd9c) acpi-build.c (7dc847ebba953db90853d15f140c20eef74d4fb2)
1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *

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86#define ACPI_BUILD_IOAPIC_ID 0x0
87
88typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91} AcpiMcfgInfo;
92
93typedef struct AcpiPmInfo {
1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *

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86#define ACPI_BUILD_IOAPIC_ID 0x0
87
88typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91} AcpiMcfgInfo;
92
93typedef struct AcpiPmInfo {
94 bool force_rev1_fadt;
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 uint8_t s4_val;
98 AcpiFadtData fadt;
99 uint16_t sci_int;
100 uint8_t acpi_enable_cmd;
101 uint8_t acpi_disable_cmd;
102 uint32_t gpe0_blk;
103 uint32_t gpe0_blk_len;
104 uint32_t io_base;
99 uint16_t cpu_hp_io_base;
100 uint16_t pcihp_io_base;
101 uint16_t pcihp_io_len;
102} AcpiPmInfo;
103
104typedef struct AcpiMiscInfo {
105 bool is_piix4;
106 bool has_hpet;

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113
114typedef struct AcpiBuildPciBusHotplugState {
115 GArray *device_table;
116 GArray *notify_table;
117 struct AcpiBuildPciBusHotplugState *parent;
118 bool pcihp_bridge_en;
119} AcpiBuildPciBusHotplugState;
120
105 uint16_t cpu_hp_io_base;
106 uint16_t pcihp_io_base;
107 uint16_t pcihp_io_len;
108} AcpiPmInfo;
109
110typedef struct AcpiMiscInfo {
111 bool is_piix4;
112 bool has_hpet;

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119
120typedef struct AcpiBuildPciBusHotplugState {
121 GArray *device_table;
122 GArray *notify_table;
123 struct AcpiBuildPciBusHotplugState *parent;
124 bool pcihp_bridge_en;
125} AcpiBuildPciBusHotplugState;
126
121static void init_common_fadt_data(Object *o, AcpiFadtData *data)
122{
123 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
124 AmlAddressSpace as = AML_AS_SYSTEM_IO;
125 AcpiFadtData fadt = {
126 .rev = 3,
127 .flags =
128 (1 << ACPI_FADT_F_WBINVD) |
129 (1 << ACPI_FADT_F_PROC_C1) |
130 (1 << ACPI_FADT_F_SLP_BUTTON) |
131 (1 << ACPI_FADT_F_RTC_S4) |
132 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
133 /* APIC destination mode ("Flat Logical") has an upper limit of 8
134 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
135 * used
136 */
137 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
138 .int_model = 1 /* Multiple APIC */,
139 .rtc_century = RTC_CENTURY,
140 .plvl2_lat = 0xfff /* C2 state not supported */,
141 .plvl3_lat = 0xfff /* C3 state not supported */,
142 .smi_cmd = ACPI_PORT_SMI_CMD,
143 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
144 .acpi_enable_cmd =
145 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
146 .acpi_disable_cmd =
147 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
148 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
149 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
150 .address = io + 0x04 },
151 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
152 .gpe0_blk = { .space_id = as, .bit_width =
153 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
154 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
155 },
156 };
157 *data = fadt;
158}
159
160static void acpi_get_pm_info(AcpiPmInfo *pm)
161{
162 Object *piix = piix4_pm_find();
163 Object *lpc = ich9_lpc_find();
127static void acpi_get_pm_info(AcpiPmInfo *pm)
128{
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
164 Object *obj = piix ? piix : lpc;
131 Object *obj = NULL;
165 QObject *o;
132 QObject *o;
133
134 pm->force_rev1_fadt = false;
166 pm->cpu_hp_io_base = 0;
167 pm->pcihp_io_base = 0;
168 pm->pcihp_io_len = 0;
135 pm->cpu_hp_io_base = 0;
136 pm->pcihp_io_base = 0;
137 pm->pcihp_io_len = 0;
169
170 init_common_fadt_data(obj, &pm->fadt);
171 if (piix) {
172 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
138 if (piix) {
139 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
173 pm->fadt.rev = 1;
140 pm->force_rev1_fadt = true;
141 obj = piix;
174 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
175 pm->pcihp_io_base =
176 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
177 pm->pcihp_io_len =
178 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
179 }
180 if (lpc) {
142 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
143 pm->pcihp_io_base =
144 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
145 pm->pcihp_io_len =
146 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
147 }
148 if (lpc) {
181 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
182 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
183 pm->fadt.reset_reg = r;
184 pm->fadt.reset_val = 0xf;
185 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
149 obj = lpc;
186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
187 }
188 assert(obj);
189
150 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
151 }
152 assert(obj);
153
190 /* The above need not be conditional on machine type because the reset port
191 * happens to be the same on PIIX (pc) and ICH9 (q35). */
192 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
193
194 /* Fill in optional s3/s4 related properties */
195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
196 if (o) {
154 /* Fill in optional s3/s4 related properties */
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
156 if (o) {
197 pm->s3_disabled = qnum_get_uint(qobject_to_qnum(o));
157 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
198 } else {
199 pm->s3_disabled = false;
200 }
201 qobject_decref(o);
202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
203 if (o) {
158 } else {
159 pm->s3_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
163 if (o) {
204 pm->s4_disabled = qnum_get_uint(qobject_to_qnum(o));
164 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
205 } else {
206 pm->s4_disabled = false;
207 }
208 qobject_decref(o);
209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
210 if (o) {
165 } else {
166 pm->s4_disabled = false;
167 }
168 qobject_decref(o);
169 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
170 if (o) {
211 pm->s4_val = qnum_get_uint(qobject_to_qnum(o));
171 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
212 } else {
213 pm->s4_val = false;
214 }
215 qobject_decref(o);
216
172 } else {
173 pm->s4_val = false;
174 }
175 qobject_decref(o);
176
177 /* Fill in mandatory properties */
178 pm->sci_int = object_property_get_uint(obj, ACPI_PM_PROP_SCI_INT, NULL);
179
180 pm->acpi_enable_cmd = object_property_get_uint(obj,
181 ACPI_PM_PROP_ACPI_ENABLE_CMD,
182 NULL);
183 pm->acpi_disable_cmd =
184 object_property_get_uint(obj,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD,
186 NULL);
187 pm->io_base = object_property_get_uint(obj, ACPI_PM_PROP_PM_IO_BASE,
188 NULL);
189 pm->gpe0_blk = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK,
190 NULL);
191 pm->gpe0_blk_len = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
192 NULL);
217 pm->pcihp_bridge_en =
218 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
219 NULL);
220}
221
222static void acpi_get_misc_info(AcpiMiscInfo *info)
223{
224 Object *piix = piix4_pm_find();

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276 object_property_get_uint(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_START,
278 NULL),
279 object_property_get_uint(pci_host,
280 PCI_HOST_PROP_PCI_HOLE64_END,
281 NULL));
282}
283
193 pm->pcihp_bridge_en =
194 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
195 NULL);
196}
197
198static void acpi_get_misc_info(AcpiMiscInfo *info)
199{
200 Object *piix = piix4_pm_find();

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252 object_property_get_uint(pci_host,
253 PCI_HOST_PROP_PCI_HOLE64_START,
254 NULL),
255 object_property_get_uint(pci_host,
256 PCI_HOST_PROP_PCI_HOLE64_END,
257 NULL));
258}
259
260#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
261
284static void acpi_align_size(GArray *blob, unsigned align)
285{
286 /* Align size to multiple of given size. This reduces the chance
287 * we need to change size in the future (breaking cross version migration).
288 */
289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
290}
291
292/* FACS */
293static void
294build_facs(GArray *table_data, BIOSLinker *linker)
295{
296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
297 memcpy(&facs->signature, "FACS", 4);
298 facs->length = cpu_to_le32(sizeof(*facs));
299}
300
262static void acpi_align_size(GArray *blob, unsigned align)
263{
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
266 */
267 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
268}
269
270/* FACS */
271static void
272build_facs(GArray *table_data, BIOSLinker *linker)
273{
274 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
275 memcpy(&facs->signature, "FACS", 4);
276 facs->length = cpu_to_le32(sizeof(*facs));
277}
278
279/* Load chipset information in FADT */
280static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm)
281{
282 fadt->model = 1;
283 fadt->reserved1 = 0;
284 fadt->sci_int = cpu_to_le16(pm->sci_int);
285 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
286 fadt->acpi_enable = pm->acpi_enable_cmd;
287 fadt->acpi_disable = pm->acpi_disable_cmd;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
290 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
291 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
292 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt->pm1_evt_len = 4;
295 fadt->pm1_cnt_len = 2;
296 fadt->pm_tmr_len = 4;
297 fadt->gpe0_blk_len = pm->gpe0_blk_len;
298 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
301 (1 << ACPI_FADT_F_PROC_C1) |
302 (1 << ACPI_FADT_F_SLP_BUTTON) |
303 (1 << ACPI_FADT_F_RTC_S4));
304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
307 */
308 if (max_cpus > 8) {
309 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
310 }
311 fadt->century = RTC_CENTURY;
312 if (pm->force_rev1_fadt) {
313 return;
314 }
315
316 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP);
317 fadt->reset_value = 0xf;
318 fadt->reset_register.space_id = AML_SYSTEM_IO;
319 fadt->reset_register.bit_width = 8;
320 fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT);
321 /* The above need not be conditional on machine type because the reset port
322 * happens to be the same on PIIX (pc) and ICH9 (q35). */
323 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
324
325 fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO;
326 fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8;
327 fadt->xpm1a_event_block.address = cpu_to_le64(pm->io_base);
328
329 fadt->xpm1a_control_block.space_id = AML_SYSTEM_IO;
330 fadt->xpm1a_control_block.bit_width = fadt->pm1_cnt_len * 8;
331 fadt->xpm1a_control_block.address = cpu_to_le64(pm->io_base + 0x4);
332
333 fadt->xpm_timer_block.space_id = AML_SYSTEM_IO;
334 fadt->xpm_timer_block.bit_width = fadt->pm_tmr_len * 8;
335 fadt->xpm_timer_block.address = cpu_to_le64(pm->io_base + 0x8);
336
337 fadt->xgpe0_block.space_id = AML_SYSTEM_IO;
338 fadt->xgpe0_block.bit_width = pm->gpe0_blk_len * 8;
339 fadt->xgpe0_block.address = cpu_to_le64(pm->gpe0_blk);
340}
341
342
343/* FADT */
344static void
345build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
346 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
347 const char *oem_id, const char *oem_table_id)
348{
349 AcpiFadtDescriptorRev3 *fadt = acpi_data_push(table_data, sizeof(*fadt));
350 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
351 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
352 unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data;
353 int fadt_size = sizeof(*fadt);
354 int rev = 3;
355
356 /* FACS address to be filled by Guest linker */
357 bios_linker_loader_add_pointer(linker,
358 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
359 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
360
361 /* DSDT address to be filled by Guest linker */
362 fadt_setup(fadt, pm);
363 bios_linker_loader_add_pointer(linker,
364 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
365 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
366 if (pm->force_rev1_fadt) {
367 rev = 1;
368 fadt_size = offsetof(typeof(*fadt), reset_register);
369 } else {
370 bios_linker_loader_add_pointer(linker,
371 ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt),
372 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
373 }
374
375 build_header(linker, table_data,
376 (void *)fadt, "FACP", fadt_size, rev, oem_id, oem_table_id);
377}
378
301void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
302 const CPUArchIdList *apic_ids, GArray *entry)
303{
304 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
305
306 /* ACPI spec says that LAPIC entry for non present
307 * CPU may be omitted from MADT or it must be marked
308 * as disabled. However omitting non present CPU from

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424 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
425 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
426 aml_append(method, if_ctx);
427}
428
429static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
430 bool pcihp_bridge_en)
431{
379void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
380 const CPUArchIdList *apic_ids, GArray *entry)
381{
382 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
383
384 /* ACPI spec says that LAPIC entry for non present
385 * CPU may be omitted from MADT or it must be marked
386 * as disabled. However omitting non present CPU from

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502 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
503 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
504 aml_append(method, if_ctx);
505}
506
507static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
508 bool pcihp_bridge_en)
509{
432 Aml *dev, *notify_method, *method;
510 Aml *dev, *notify_method = NULL, *method;
433 QObject *bsel;
434 PCIBus *sec;
435 int i;
436
437 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
438 if (bsel) {
511 QObject *bsel;
512 PCIBus *sec;
513 int i;
514
515 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
516 if (bsel) {
439 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
517 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
440
441 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
442 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
443 }
444
445 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
446 DeviceClass *dc;
447 PCIDeviceClass *pc;

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541
542 /* Append PCNT method to notify about events on local and child buses.
543 * Add unconditionally for root since DSDT expects it.
544 */
545 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
546
547 /* If bus supports hotplug select it and notify about local events */
548 if (bsel) {
518
519 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
520 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
521 }
522
523 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
524 DeviceClass *dc;
525 PCIDeviceClass *pc;

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619
620 /* Append PCNT method to notify about events on local and child buses.
621 * Add unconditionally for root since DSDT expects it.
622 */
623 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
624
625 /* If bus supports hotplug select it and notify about local events */
626 if (bsel) {
549 uint64_t bsel_val = qnum_get_uint(qobject_to_qnum(bsel));
627 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
550
551 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
552 aml_append(method,
553 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
554 );
555 aml_append(method,
556 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
557 );

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1970 /* reserve GPE0 block resources */
1971 dev = aml_device("GPE0");
1972 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1973 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1974 /* device present, functioning, decoding, not shown in UI */
1975 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1976 crs = aml_resource_template();
1977 aml_append(crs,
628
629 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
630 aml_append(method,
631 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
632 );
633 aml_append(method,
634 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
635 );

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2048 /* reserve GPE0 block resources */
2049 dev = aml_device("GPE0");
2050 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2051 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2052 /* device present, functioning, decoding, not shown in UI */
2053 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2054 crs = aml_resource_template();
2055 aml_append(crs,
1978 aml_io(
1979 AML_DECODE16,
1980 pm->fadt.gpe0_blk.address,
1981 pm->fadt.gpe0_blk.address,
1982 1,
1983 pm->fadt.gpe0_blk.bit_width / 8)
2056 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1984 );
1985 aml_append(dev, aml_name_decl("_CRS", crs));
1986 aml_append(scope, dev);
1987
1988 crs_range_set_free(&crs_range_set);
1989
1990 /* reserve PCIHP resources */
1991 if (pm->pcihp_io_len) {

--- 568 unchanged lines hidden (view full) ---

2560
2561 pci_host = acpi_get_i386_pci_host();
2562 g_assert(pci_host);
2563
2564 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2565 if (!o) {
2566 return false;
2567 }
2057 );
2058 aml_append(dev, aml_name_decl("_CRS", crs));
2059 aml_append(scope, dev);
2060
2061 crs_range_set_free(&crs_range_set);
2062
2063 /* reserve PCIHP resources */
2064 if (pm->pcihp_io_len) {

--- 568 unchanged lines hidden (view full) ---

2633
2634 pci_host = acpi_get_i386_pci_host();
2635 g_assert(pci_host);
2636
2637 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2638 if (!o) {
2639 return false;
2640 }
2568 mcfg->mcfg_base = qnum_get_uint(qobject_to_qnum(o));
2641 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
2569 qobject_decref(o);
2570
2571 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2572 assert(o);
2642 qobject_decref(o);
2643
2644 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2645 assert(o);
2573 mcfg->mcfg_size = qnum_get_uint(qobject_to_qnum(o));
2646 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
2574 qobject_decref(o);
2575 return true;
2576}
2577
2578static
2579void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2580{
2581 PCMachineState *pcms = PC_MACHINE(machine);

--- 40 unchanged lines hidden (view full) ---

2622 /* Count the size of the DSDT and SSDT, we will need it for legacy
2623 * sizing of ACPI tables.
2624 */
2625 aml_len += tables_blob->len - dsdt;
2626
2627 /* ACPI tables pointed to by RSDT */
2628 fadt = tables_blob->len;
2629 acpi_add_table(table_offsets, tables_blob);
2647 qobject_decref(o);
2648 return true;
2649}
2650
2651static
2652void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2653{
2654 PCMachineState *pcms = PC_MACHINE(machine);

--- 40 unchanged lines hidden (view full) ---

2695 /* Count the size of the DSDT and SSDT, we will need it for legacy
2696 * sizing of ACPI tables.
2697 */
2698 aml_len += tables_blob->len - dsdt;
2699
2700 /* ACPI tables pointed to by RSDT */
2701 fadt = tables_blob->len;
2702 acpi_add_table(table_offsets, tables_blob);
2630 pm.fadt.facs_tbl_offset = &facs;
2631 pm.fadt.dsdt_tbl_offset = &dsdt;
2632 pm.fadt.xdsdt_tbl_offset = &dsdt;
2633 build_fadt(tables_blob, tables->linker, &pm.fadt,
2703 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2634 slic_oem.id, slic_oem.table_id);
2635 aml_len += tables_blob->len - fadt;
2636
2637 acpi_add_table(table_offsets, tables_blob);
2638 build_madt(tables_blob, tables->linker, pcms);
2639
2640 vmgenid_dev = find_vmgenid_dev();
2641 if (vmgenid_dev) {

--- 253 unchanged lines hidden --- 		2704 slic_oem.id, slic_oem.table_id);
2705 aml_len += tables_blob->len - fadt;
2706
2707 acpi_add_table(table_offsets, tables_blob);
2708 build_madt(tables_blob, tables->linker, pcms);
2709
2710 vmgenid_dev = find_vmgenid_dev();
2711 if (vmgenid_dev) {

--- 253 unchanged lines hidden ---