acpi-build.c (33e60e01988b02ac9baf4dc0f4a452b39fb5ce55) acpi-build.c (fb9f592623b0f9bb82a88d68d7921fb581918ef5)
1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *

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54#include "hw/pci-host/q35.h"
55#include "hw/i386/x86-iommu.h"
56#include "hw/timer/hpet.h"
57
58#include "hw/acpi/aml-build.h"
59
60#include "qapi/qmp/qint.h"
61#include "qom/qom-qobject.h"
1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *

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54#include "hw/pci-host/q35.h"
55#include "hw/i386/x86-iommu.h"
56#include "hw/timer/hpet.h"
57
58#include "hw/acpi/aml-build.h"
59
60#include "qapi/qmp/qint.h"
61#include "qom/qom-qobject.h"
62#include "hw/i386/x86-iommu.h"
62#include "hw/i386/amd_iommu.h"
63#include "hw/i386/intel_iommu.h"
63
64#include "hw/acpi/ipmi.h"
65
66/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */

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2557 scope->length = ioapic_scope_size;
2558 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2559 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2560 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2561
2562 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2563 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2564}
64
65#include "hw/acpi/ipmi.h"
66
67/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */

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2558 scope->length = ioapic_scope_size;
2559 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2560 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2561 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2562
2563 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2564 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2565}
2566/*
2567 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2568 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2569 */
2570static void
2571build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2572{
2573 int iommu_start = table_data->len;
2574 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2565
2575
2576 /* IVRS header */
2577 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2578 /* IVinfo - IO virtualization information common to all
2579 * IOMMU units in a system
2580 */
2581 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2582 /* reserved */
2583 build_append_int_noprefix(table_data, 0, 8);
2584
2585 /* IVHD definition - type 10h */
2586 build_append_int_noprefix(table_data, 0x10, 1);
2587 /* virtualization flags */
2588 build_append_int_noprefix(table_data,
2589 (1UL << 0) | /* HtTunEn */
2590 (1UL << 4) | /* iotblSup */
2591 (1UL << 6) | /* PrefSup */
2592 (1UL << 7), /* PPRSup */
2593 1);
2594 /* IVHD length */
2595 build_append_int_noprefix(table_data, 0x24, 2);
2596 /* DeviceID */
2597 build_append_int_noprefix(table_data, s->devid, 2);
2598 /* Capability offset */
2599 build_append_int_noprefix(table_data, s->capab_offset, 2);
2600 /* IOMMU base address */
2601 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2602 /* PCI Segment Group */
2603 build_append_int_noprefix(table_data, 0, 2);
2604 /* IOMMU info */
2605 build_append_int_noprefix(table_data, 0, 2);
2606 /* IOMMU Feature Reporting */
2607 build_append_int_noprefix(table_data,
2608 (48UL << 30) | /* HATS */
2609 (48UL << 28) | /* GATS */
2610 (1UL << 2), /* GTSup */
2611 4);
2612 /*
2613 * Type 1 device entry reporting all devices
2614 * These are 4-byte device entries currently reporting the range of
2615 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2616 */
2617 build_append_int_noprefix(table_data, 0x0000001, 4);
2618
2619 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2620 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2621}
2622
2566static GArray *
2567build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2568{
2569 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2570 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2571 unsigned rsdt_pa_offset =
2572 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2573

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2617
2618 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2619 assert(o);
2620 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2621 qobject_decref(o);
2622 return true;
2623}
2624
2623static GArray *
2624build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2625{
2626 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2627 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2628 unsigned rsdt_pa_offset =
2629 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2630

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2674
2675 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2676 assert(o);
2677 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2678 qobject_decref(o);
2679 return true;
2680}
2681
2625static bool acpi_has_iommu(void)
2626{
2627 return !!x86_iommu_get_default();
2628}
2629
2630static
2631void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2632{
2633 PCMachineState *pcms = PC_MACHINE(machine);
2634 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2635 GArray *table_offsets;
2636 unsigned facs, dsdt, rsdt, fadt;
2637 AcpiPmInfo pm;

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2701 if (pcms->numa_nodes) {
2702 acpi_add_table(table_offsets, tables_blob);
2703 build_srat(tables_blob, tables->linker, machine);
2704 }
2705 if (acpi_get_mcfg(&mcfg)) {
2706 acpi_add_table(table_offsets, tables_blob);
2707 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2708 }
2682static
2683void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2684{
2685 PCMachineState *pcms = PC_MACHINE(machine);
2686 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2687 GArray *table_offsets;
2688 unsigned facs, dsdt, rsdt, fadt;
2689 AcpiPmInfo pm;

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2753 if (pcms->numa_nodes) {
2754 acpi_add_table(table_offsets, tables_blob);
2755 build_srat(tables_blob, tables->linker, machine);
2756 }
2757 if (acpi_get_mcfg(&mcfg)) {
2758 acpi_add_table(table_offsets, tables_blob);
2759 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2760 }
2709 if (acpi_has_iommu()) {
2710 acpi_add_table(table_offsets, tables_blob);
2711 build_dmar_q35(tables_blob, tables->linker);
2761 if (x86_iommu_get_default()) {
2762 IommuType IOMMUType = x86_iommu_get_type();
2763 if (IOMMUType == TYPE_AMD) {
2764 acpi_add_table(table_offsets, tables_blob);
2765 build_amd_iommu(tables_blob, tables->linker);
2766 } else if (IOMMUType == TYPE_INTEL) {
2767 acpi_add_table(table_offsets, tables_blob);
2768 build_dmar_q35(tables_blob, tables->linker);
2769 }
2712 }
2713 if (pcms->acpi_nvdimm_state.is_enabled) {
2714 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2715 pcms->acpi_nvdimm_state.dsm_mem);
2716 }
2717
2718 /* Add tables supplied by user (if any) */
2719 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {

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2771 if (pcms->acpi_nvdimm_state.is_enabled) {
2772 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2773 pcms->acpi_nvdimm_state.dsm_mem);
2774 }
2775
2776 /* Add tables supplied by user (if any) */
2777 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {

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