ppc4xx_i2c.c (0094908375d280c1a4e8b932d8b133a41fb3bdf8) ppc4xx_i2c.c (41742927ee37527462a13160380860653d4f1c84)
1/*
2 * PPC4xx I2C controller emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 François Revol
6 * Copyright (c) 2016-2018 BALATON Zoltan
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy

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306 /* Is it actually a full reset? U-Boot sets some regs before */
307 ppc4xx_i2c_reset(DEVICE(i2c));
308 break;
309 }
310 break;
311 case IIC_DIRECTCNTL:
312 i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);
313 i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);
1/*
2 * PPC4xx I2C controller emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 François Revol
6 * Copyright (c) 2016-2018 BALATON Zoltan
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy

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306 /* Is it actually a full reset? U-Boot sets some regs before */
307 ppc4xx_i2c_reset(DEVICE(i2c));
308 break;
309 }
310 break;
311 case IIC_DIRECTCNTL:
312 i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);
313 i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);
314 bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SCL,
314 bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SCL,
315 i2c->directcntl & IIC_DIRECTCNTL_MSCL);
315 i2c->directcntl & IIC_DIRECTCNTL_MSCL);
316 i2c->directcntl |= bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SDA,
316 i2c->directcntl |= bitbang_i2c_set(&i2c->bitbang, BITBANG_I2C_SDA,
317 (value & IIC_DIRECTCNTL_SDAC) != 0) << 1;
318 break;
319 default:
320 if (addr < PPC4xx_I2C_MEM_SIZE) {
321 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
322 HWADDR_PRIx "\n", __func__, addr);
323 } else {
324 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"

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342{
343 PPC4xxI2CState *s = PPC4xx_I2C(o);
344
345 memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
346 TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
347 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
348 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
349 s->bus = i2c_init_bus(DEVICE(s), "i2c");
317 (value & IIC_DIRECTCNTL_SDAC) != 0) << 1;
318 break;
319 default:
320 if (addr < PPC4xx_I2C_MEM_SIZE) {
321 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
322 HWADDR_PRIx "\n", __func__, addr);
323 } else {
324 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"

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342{
343 PPC4xxI2CState *s = PPC4xx_I2C(o);
344
345 memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
346 TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
347 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
348 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
349 s->bus = i2c_init_bus(DEVICE(s), "i2c");
350 s->bitbang = bitbang_i2c_init(s->bus);
350 bitbang_i2c_init(&s->bitbang, s->bus);
351}
352
353static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
354{
355 DeviceClass *dc = DEVICE_CLASS(klass);
356
357 dc->reset = ppc4xx_i2c_reset;
358}

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351}
352
353static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
354{
355 DeviceClass *dc = DEVICE_CLASS(klass);
356
357 dc->reset = ppc4xx_i2c_reset;
358}

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