bcm2835_dma.c (95a9457fd44ad97c518858a4e1586a5498f9773c) bcm2835_dma.c (e1ecf8c8026fc1b1a742160e69c0ab3087bc2841)
1/*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * This code is licensed under the GNU GPLv2 and later.
4 */
5
6#include "qemu/osdep.h"
7#include "qapi/error.h"
8#include "hw/dma/bcm2835_dma.h"

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175 break;
176 case BCM2708_DMA_NEXTCB:
177 res = ch->nextconbk;
178 break;
179 case BCM2708_DMA_DEBUG:
180 res = ch->debug;
181 break;
182 default:
1/*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * This code is licensed under the GNU GPLv2 and later.
4 */
5
6#include "qemu/osdep.h"
7#include "qapi/error.h"
8#include "hw/dma/bcm2835_dma.h"

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175 break;
176 case BCM2708_DMA_NEXTCB:
177 res = ch->nextconbk;
178 break;
179 case BCM2708_DMA_DEBUG:
180 res = ch->debug;
181 break;
182 default:
183 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
183 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
184 __func__, offset);
185 break;
186 }
187 return res;
188}
189
190static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
191 uint64_t value, unsigned size, unsigned c)

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223 break;
224 case BCM2708_DMA_ADDR:
225 ch->conblk_ad = value;
226 break;
227 case BCM2708_DMA_DEBUG:
228 ch->debug = value;
229 break;
230 default:
184 __func__, offset);
185 break;
186 }
187 return res;
188}
189
190static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
191 uint64_t value, unsigned size, unsigned c)

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223 break;
224 case BCM2708_DMA_ADDR:
225 ch->conblk_ad = value;
226 break;
227 case BCM2708_DMA_DEBUG:
228 ch->debug = value;
229 break;
230 default:
231 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
231 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
232 __func__, offset);
233 break;
234 }
235}
236
237static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
238{
239 BCM2835DMAState *s = opaque;
240
241 if (offset < 0xf00) {
242 return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
243 } else {
244 switch (offset) {
245 case BCM2708_DMA_INT_STATUS:
246 return s->int_status;
247 case BCM2708_DMA_ENABLE:
248 return s->enable;
249 default:
232 __func__, offset);
233 break;
234 }
235}
236
237static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
238{
239 BCM2835DMAState *s = opaque;
240
241 if (offset < 0xf00) {
242 return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
243 } else {
244 switch (offset) {
245 case BCM2708_DMA_INT_STATUS:
246 return s->int_status;
247 case BCM2708_DMA_ENABLE:
248 return s->enable;
249 default:
250 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
250 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
251 __func__, offset);
252 return 0;
253 }
254 }
255}
256
257static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
258{

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269 } else {
270 switch (offset) {
271 case BCM2708_DMA_INT_STATUS:
272 break;
273 case BCM2708_DMA_ENABLE:
274 s->enable = (value & 0xffff);
275 break;
276 default:
251 __func__, offset);
252 return 0;
253 }
254 }
255}
256
257static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
258{

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269 } else {
270 switch (offset) {
271 case BCM2708_DMA_INT_STATUS:
272 break;
273 case BCM2708_DMA_ENABLE:
274 s->enable = (value & 0xffff);
275 break;
276 default:
277 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
277 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
278 __func__, offset);
279 }
280 }
281
282}
283
284static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
285 unsigned size)

--- 128 unchanged lines hidden --- 		278 __func__, offset);
279 }
280 }
281
282}
283
284static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
285 unsigned size)

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