arm11mpcore.c (e0175b71638cf4398903c0d25f93fe62e0606389) arm11mpcore.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * ARM11MPCore internal peripheral emulation.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */

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74 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
75 DeviceState *scudev = DEVICE(&s->scu);
76 DeviceState *gicdev = DEVICE(&s->gic);
77 DeviceState *mptimerdev = DEVICE(&s->mptimer);
78 DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
79 Error *err = NULL;
80
81 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
1/*
2 * ARM11MPCore internal peripheral emulation.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */

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74 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
75 DeviceState *scudev = DEVICE(&s->scu);
76 DeviceState *gicdev = DEVICE(&s->gic);
77 DeviceState *mptimerdev = DEVICE(&s->mptimer);
78 DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
79 Error *err = NULL;
80
81 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
82 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
82 sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
83 if (err != NULL) {
84 error_propagate(errp, err);
85 return;
86 }
87
88 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
89 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
90 qdev_prop_set_uint32(gicdev, "num-priority-bits",
91 ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
92
93
83 if (err != NULL) {
84 error_propagate(errp, err);
85 return;
86 }
87
88 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
89 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
90 qdev_prop_set_uint32(gicdev, "num-priority-bits",
91 ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
92
93
94 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
94 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
95 if (err != NULL) {
96 error_propagate(errp, err);
97 return;
98 }
99
100 /* Pass through outbound IRQ lines from the GIC */
101 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
102
103 /* Pass through inbound GPIO lines to the GIC */
104 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
105
106 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
95 if (err != NULL) {
96 error_propagate(errp, err);
97 return;
98 }
99
100 /* Pass through outbound IRQ lines from the GIC */
101 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
102
103 /* Pass through inbound GPIO lines to the GIC */
104 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
105
106 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
107 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
107 sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
108 if (err != NULL) {
109 error_propagate(errp, err);
110 return;
111 }
112
113 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
108 if (err != NULL) {
109 error_propagate(errp, err);
110 return;
111 }
112
113 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
114 object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
114 sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err);
115 if (err != NULL) {
116 error_propagate(errp, err);
117 return;
118 }
119
120 mpcore_priv_map_setup(s);
121}
122
123static void mpcore_priv_initfn(Object *obj)
124{
125 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
126 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
127
128 memory_region_init(&s->container, OBJECT(s),
129 "mpcore-priv-container", 0x2000);
130 sysbus_init_mmio(sbd, &s->container);
131
115 if (err != NULL) {
116 error_propagate(errp, err);
117 return;
118 }
119
120 mpcore_priv_map_setup(s);
121}
122
123static void mpcore_priv_initfn(Object *obj)
124{
125 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
126 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
127
128 memory_region_init(&s->container, OBJECT(s),
129 "mpcore-priv-container", 0x2000);
130 sysbus_init_mmio(sbd, &s->container);
131
132 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
132 object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);
133
133
134 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
134 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
135 /* Request the legacy 11MPCore GIC behaviour: */
136 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
137
135 /* Request the legacy 11MPCore GIC behaviour: */
136 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
137
138 sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
139 TYPE_ARM_MPTIMER);
138 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
140
139
141 sysbus_init_child_obj(obj, "wdtimer", &s->wdtimer, sizeof(s->wdtimer),
142 TYPE_ARM_MPTIMER);
140 object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
143}
144
145static Property mpcore_priv_properties[] = {
146 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
147 /* The ARM11 MPCORE TRM says the on-chip controller may have
148 * anything from 0 to 224 external interrupt IRQ lines (with another
149 * 32 internal). We default to 32+32, which is the number provided by
150 * the ARM11 MPCore test chip in the Realview Versatile Express

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142
143static Property mpcore_priv_properties[] = {
144 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
145 /* The ARM11 MPCORE TRM says the on-chip controller may have
146 * anything from 0 to 224 external interrupt IRQ lines (with another
147 * 32 internal). We default to 32+32, which is the number provided by
148 * the ARM11 MPCore test chip in the Realview Versatile Express

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