xilinx_zynq.c (ef475b5dd12684591e6264e517eaa5b3e90f7ffa) xilinx_zynq.c (ba1ba5cca3962a9cc400c713c736b4fb8db1f38e)
1/*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *

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153 }
154 }
155
156}
157
158static void zynq_init(MachineState *machine)
159{
160 ram_addr_t ram_size = machine->ram_size;
1/*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *

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153 }
154 }
155
156}
157
158static void zynq_init(MachineState *machine)
159{
160 ram_addr_t ram_size = machine->ram_size;
161 const char *cpu_model = machine->cpu_model;
162 const char *kernel_filename = machine->kernel_filename;
163 const char *kernel_cmdline = machine->kernel_cmdline;
164 const char *initrd_filename = machine->initrd_filename;
161 const char *kernel_filename = machine->kernel_filename;
162 const char *kernel_cmdline = machine->kernel_cmdline;
163 const char *initrd_filename = machine->initrd_filename;
165 ObjectClass *cpu_oc;
166 ARMCPU *cpu;
167 MemoryRegion *address_space_mem = get_system_memory();
168 MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
169 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
170 DeviceState *dev, *carddev;
171 SysBusDevice *busdev;
172 DriveInfo *di;
173 BlockBackend *blk;
174 qemu_irq pic[64];
175 int n;
176
164 ARMCPU *cpu;
165 MemoryRegion *address_space_mem = get_system_memory();
166 MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
167 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
168 DeviceState *dev, *carddev;
169 SysBusDevice *busdev;
170 DriveInfo *di;
171 BlockBackend *blk;
172 qemu_irq pic[64];
173 int n;
174
177 if (!cpu_model) {
178 cpu_model = "cortex-a9";
179 }
180 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
175 cpu = ARM_CPU(object_new(machine->cpu_type));
181
176
182 cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
183
184 /* By default A9 CPUs have EL3 enabled. This board does not
185 * currently support EL3 so the CPU EL3 property is disabled before
186 * realization.
187 */
188 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
189 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
190 }
191

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322
323static void zynq_machine_init(MachineClass *mc)
324{
325 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
326 mc->init = zynq_init;
327 mc->max_cpus = 1;
328 mc->no_sdcard = 1;
329 mc->ignore_memory_transaction_failures = true;
177 /* By default A9 CPUs have EL3 enabled. This board does not
178 * currently support EL3 so the CPU EL3 property is disabled before
179 * realization.
180 */
181 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
182 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
183 }
184

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315
316static void zynq_machine_init(MachineClass *mc)
317{
318 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
319 mc->init = zynq_init;
320 mc->max_cpus = 1;
321 mc->no_sdcard = 1;
322 mc->ignore_memory_transaction_failures = true;
323 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
330}
331
332DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
324}
325
326DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)