xilinx_zynq.c (940d5b132fab085bd8ec2bcfa5c1dd119785b217) xilinx_zynq.c (ce14710f4fdfca32123d7efd3ddcbee984ef0ae5)
1/*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *

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202 &error_fatal);
203 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
204
205 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
206
207 /* AMD */
208 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
209 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1/*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *

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202 &error_fatal);
203 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
204
205 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
206
207 /* AMD */
208 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
209 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
210 FLASH_SECTOR_SIZE,
211 FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
210 FLASH_SECTOR_SIZE, 1,
212 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
211 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
213 0);
212 0);
214
215 dev = qdev_create(NULL, "xilinx,zynq_slcr");
216 qdev_init_nofail(dev);
217 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
218
219 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
220 qdev_prop_set_uint32(dev, "num-cpu", 1);
221 qdev_init_nofail(dev);

--- 109 unchanged lines hidden --- 		213
214 dev = qdev_create(NULL, "xilinx,zynq_slcr");
215 qdev_init_nofail(dev);
216 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
217
218 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
219 qdev_prop_set_uint32(dev, "num-cpu", 1);
220 qdev_init_nofail(dev);

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