virt.c (d28e29a92585e94264628b1b27262fe2d7573f51) virt.c (ba1ba5cca3962a9cc400c713c736b4fb8db1f38e)
1/*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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158 [VIRT_GPIO] = 7,
159 [VIRT_SECURE_UART] = 8,
160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
163};
164
165static const char *valid_cpus[] = {
1/*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.

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158 [VIRT_GPIO] = 7,
159 [VIRT_SECURE_UART] = 8,
160 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
161 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
162 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
163};
164
165static const char *valid_cpus[] = {
166 "cortex-a15",
167 "cortex-a53",
168 "cortex-a57",
169 "host",
166 ARM_CPU_TYPE_NAME("cortex-a15"),
167 ARM_CPU_TYPE_NAME("cortex-a53"),
168 ARM_CPU_TYPE_NAME("cortex-a57"),
169 ARM_CPU_TYPE_NAME("host"),
170};
171
170};
171
172static bool cpuname_valid(const char *cpu)
172static bool cpu_type_valid(const char *cpu)
173{
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
177 if (strcmp(cpu, valid_cpus[i]) == 0) {
178 return true;
179 }
180 }

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1254 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1255 MachineClass *mc = MACHINE_GET_CLASS(machine);
1256 const CPUArchIdList *possible_cpus;
1257 qemu_irq pic[NUM_IRQS];
1258 MemoryRegion *sysmem = get_system_memory();
1259 MemoryRegion *secure_sysmem = NULL;
1260 int n, virt_max_cpus;
1261 MemoryRegion *ram = g_new(MemoryRegion, 1);
173{
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
177 if (strcmp(cpu, valid_cpus[i]) == 0) {
178 return true;
179 }
180 }

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1254 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1255 MachineClass *mc = MACHINE_GET_CLASS(machine);
1256 const CPUArchIdList *possible_cpus;
1257 qemu_irq pic[NUM_IRQS];
1258 MemoryRegion *sysmem = get_system_memory();
1259 MemoryRegion *secure_sysmem = NULL;
1260 int n, virt_max_cpus;
1261 MemoryRegion *ram = g_new(MemoryRegion, 1);
1262 const char *cpu_model = machine->cpu_model;
1263 char **cpustr;
1264 ObjectClass *oc;
1265 const char *typename;
1266 CPUClass *cc;
1267 Error *err = NULL;
1268 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1269
1262 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1263
1270 if (!cpu_model) {
1271 cpu_model = "cortex-a15";
1272 }
1273
1274 /* We can probe only here because during property set
1275 * KVM is not available yet
1276 */
1277 if (!vms->gic_version) {
1278 if (!kvm_enabled()) {
1279 error_report("gic-version=host requires KVM");
1280 exit(1);
1281 }
1282
1283 vms->gic_version = kvm_arm_vgic_probe();
1284 if (!vms->gic_version) {
1285 error_report("Unable to determine GIC version supported by host");
1286 exit(1);
1287 }
1288 }
1289
1264 /* We can probe only here because during property set
1265 * KVM is not available yet
1266 */
1267 if (!vms->gic_version) {
1268 if (!kvm_enabled()) {
1269 error_report("gic-version=host requires KVM");
1270 exit(1);
1271 }
1272
1273 vms->gic_version = kvm_arm_vgic_probe();
1274 if (!vms->gic_version) {
1275 error_report("Unable to determine GIC version supported by host");
1276 exit(1);
1277 }
1278 }
1279
1290 /* Separate the actual CPU model name from any appended features */
1291 cpustr = g_strsplit(cpu_model, ",", 2);
1292
1293 if (!cpuname_valid(cpustr[0])) {
1294 error_report("mach-virt: CPU %s not supported", cpustr[0]);
1280 if (!cpu_type_valid(machine->cpu_type)) {
1281 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1295 exit(1);
1296 }
1297
1298 /* If we have an EL3 boot ROM then the assumption is that it will
1299 * implement PSCI itself, so disable QEMU's internal implementation
1300 * so it doesn't get in the way. Instead of starting secondary
1301 * CPUs in PSCI powerdown state we will start them all running and
1302 * let the boot ROM sort them out.

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1356 secure_sysmem = g_new(MemoryRegion, 1);
1357 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1358 UINT64_MAX);
1359 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1360 }
1361
1362 create_fdt(vms);
1363
1282 exit(1);
1283 }
1284
1285 /* If we have an EL3 boot ROM then the assumption is that it will
1286 * implement PSCI itself, so disable QEMU's internal implementation
1287 * so it doesn't get in the way. Instead of starting secondary
1288 * CPUs in PSCI powerdown state we will start them all running and
1289 * let the boot ROM sort them out.

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1343 secure_sysmem = g_new(MemoryRegion, 1);
1344 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1345 UINT64_MAX);
1346 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1347 }
1348
1349 create_fdt(vms);
1350
1364 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
1365 if (!oc) {
1366 error_report("Unable to find CPU definition");
1367 exit(1);
1368 }
1369 typename = object_class_get_name(oc);
1370
1371 /* convert -smp CPU options specified by the user into global props */
1372 cc = CPU_CLASS(oc);
1373 cc->parse_features(typename, cpustr[1], &err);
1374 g_strfreev(cpustr);
1375 if (err) {
1376 error_report_err(err);
1377 exit(1);
1378 }
1379
1380 possible_cpus = mc->possible_cpu_arch_ids(machine);
1381 for (n = 0; n < possible_cpus->len; n++) {
1382 Object *cpuobj;
1383 CPUState *cs;
1384
1385 if (n >= smp_cpus) {
1386 break;
1387 }
1388
1351 possible_cpus = mc->possible_cpu_arch_ids(machine);
1352 for (n = 0; n < possible_cpus->len; n++) {
1353 Object *cpuobj;
1354 CPUState *cs;
1355
1356 if (n >= smp_cpus) {
1357 break;
1358 }
1359
1389 cpuobj = object_new(typename);
1360 cpuobj = object_new(machine->cpu_type);
1390 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1391 "mp-affinity", NULL);
1392
1393 cs = CPU(cpuobj);
1394 cs->cpu_index = n;
1395
1396 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1397 &error_fatal);

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1626 mc->has_dynamic_sysbus = true;
1627 mc->block_default_type = IF_VIRTIO;
1628 mc->no_cdrom = 1;
1629 mc->pci_allow_0_address = true;
1630 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1631 mc->minimum_page_bits = 12;
1632 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1633 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1361 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1362 "mp-affinity", NULL);
1363
1364 cs = CPU(cpuobj);
1365 cs->cpu_index = n;
1366
1367 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1368 &error_fatal);

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1597 mc->has_dynamic_sysbus = true;
1598 mc->block_default_type = IF_VIRTIO;
1599 mc->no_cdrom = 1;
1600 mc->pci_allow_0_address = true;
1601 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1602 mc->minimum_page_bits = 12;
1603 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1604 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1605 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1634}
1635
1636static const TypeInfo virt_machine_info = {
1637 .name = TYPE_VIRT_MACHINE,
1638 .parent = TYPE_MACHINE,
1639 .abstract = true,
1640 .instance_size = sizeof(VirtMachineState),
1641 .class_size = sizeof(VirtMachineClass),

--- 150 unchanged lines hidden --- 		1606}
1607
1608static const TypeInfo virt_machine_info = {
1609 .name = TYPE_VIRT_MACHINE,
1610 .parent = TYPE_MACHINE,
1611 .abstract = true,
1612 .instance_size = sizeof(VirtMachineState),
1613 .class_size = sizeof(VirtMachineClass),

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