stm32f405_soc.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) stm32f405_soc.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * STM32F405 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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52 40, 40, 40, 40, 40} ;
53
54
55static void stm32f405_soc_initfn(Object *obj)
56{
57 STM32F405State *s = STM32F405_SOC(obj);
58 int i;
59
1/*
2 * STM32F405 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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52 40, 40, 40, 40, 40} ;
53
54
55static void stm32f405_soc_initfn(Object *obj)
56{
57 STM32F405State *s = STM32F405_SOC(obj);
58 int i;
59
60 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
61 TYPE_ARMV7M);
60 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
62
61
63 sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
64 TYPE_STM32F4XX_SYSCFG);
62 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
65
66 for (i = 0; i < STM_NUM_USARTS; i++) {
63
64 for (i = 0; i < STM_NUM_USARTS; i++) {
67 sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
68 sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
65 object_initialize_child(obj, "usart[*]", &s->usart[i],
66 TYPE_STM32F2XX_USART);
69 }
70
71 for (i = 0; i < STM_NUM_TIMERS; i++) {
67 }
68
69 for (i = 0; i < STM_NUM_TIMERS; i++) {
72 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
73 sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
70 object_initialize_child(obj, "timer[*]", &s->timer[i],
71 TYPE_STM32F2XX_TIMER);
74 }
75
76 for (i = 0; i < STM_NUM_ADCS; i++) {
72 }
73
74 for (i = 0; i < STM_NUM_ADCS; i++) {
77 sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
78 TYPE_STM32F2XX_ADC);
75 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
79 }
80
81 for (i = 0; i < STM_NUM_SPIS; i++) {
76 }
77
78 for (i = 0; i < STM_NUM_SPIS; i++) {
82 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
83 TYPE_STM32F2XX_SPI);
79 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
84 }
85
80 }
81
86 sysbus_init_child_obj(obj, "exti", &s->exti, sizeof(s->exti),
87 TYPE_STM32F4XX_EXTI);
82 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
88}
89
90static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
91{
92 STM32F405State *s = STM32F405_SOC(dev_soc);
93 MemoryRegion *system_memory = get_system_memory();
94 DeviceState *dev, *armv7m;
95 SysBusDevice *busdev;

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118 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
119
120 armv7m = DEVICE(&s->armv7m);
121 qdev_prop_set_uint32(armv7m, "num-irq", 96);
122 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
123 qdev_prop_set_bit(armv7m, "enable-bitband", true);
124 object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
125 "memory", &error_abort);
83}
84
85static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
86{
87 STM32F405State *s = STM32F405_SOC(dev_soc);
88 MemoryRegion *system_memory = get_system_memory();
89 DeviceState *dev, *armv7m;
90 SysBusDevice *busdev;

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113 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
114
115 armv7m = DEVICE(&s->armv7m);
116 qdev_prop_set_uint32(armv7m, "num-irq", 96);
117 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
118 qdev_prop_set_bit(armv7m, "enable-bitband", true);
119 object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
120 "memory", &error_abort);
126 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
121 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
127 if (err != NULL) {
128 error_propagate(errp, err);
129 return;
130 }
131
132 /* System configuration controller */
133 dev = DEVICE(&s->syscfg);
122 if (err != NULL) {
123 error_propagate(errp, err);
124 return;
125 }
126
127 /* System configuration controller */
128 dev = DEVICE(&s->syscfg);
134 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
129 sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
135 if (err != NULL) {
136 error_propagate(errp, err);
137 return;
138 }
139 busdev = SYS_BUS_DEVICE(dev);
140 sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
141 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
142
143 /* Attach UART (uses USART registers) and USART controllers */
144 for (i = 0; i < STM_NUM_USARTS; i++) {
145 dev = DEVICE(&(s->usart[i]));
146 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
130 if (err != NULL) {
131 error_propagate(errp, err);
132 return;
133 }
134 busdev = SYS_BUS_DEVICE(dev);
135 sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
136 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
137
138 /* Attach UART (uses USART registers) and USART controllers */
139 for (i = 0; i < STM_NUM_USARTS; i++) {
140 dev = DEVICE(&(s->usart[i]));
141 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
147 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
142 sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
148 if (err != NULL) {
149 error_propagate(errp, err);
150 return;
151 }
152 busdev = SYS_BUS_DEVICE(dev);
153 sysbus_mmio_map(busdev, 0, usart_addr[i]);
154 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
155 }
156
157 /* Timer 2 to 5 */
158 for (i = 0; i < STM_NUM_TIMERS; i++) {
159 dev = DEVICE(&(s->timer[i]));
160 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
143 if (err != NULL) {
144 error_propagate(errp, err);
145 return;
146 }
147 busdev = SYS_BUS_DEVICE(dev);
148 sysbus_mmio_map(busdev, 0, usart_addr[i]);
149 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
150 }
151
152 /* Timer 2 to 5 */
153 for (i = 0; i < STM_NUM_TIMERS; i++) {
154 dev = DEVICE(&(s->timer[i]));
155 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
161 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
156 sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
162 if (err != NULL) {
163 error_propagate(errp, err);
164 return;
165 }
166 busdev = SYS_BUS_DEVICE(dev);
167 sysbus_mmio_map(busdev, 0, timer_addr[i]);
168 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
169 }

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183 error_propagate(errp, err);
184 return;
185 }
186 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
187 qdev_get_gpio_in(armv7m, ADC_IRQ));
188
189 for (i = 0; i < STM_NUM_ADCS; i++) {
190 dev = DEVICE(&(s->adc[i]));
157 if (err != NULL) {
158 error_propagate(errp, err);
159 return;
160 }
161 busdev = SYS_BUS_DEVICE(dev);
162 sysbus_mmio_map(busdev, 0, timer_addr[i]);
163 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
164 }

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178 error_propagate(errp, err);
179 return;
180 }
181 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
182 qdev_get_gpio_in(armv7m, ADC_IRQ));
183
184 for (i = 0; i < STM_NUM_ADCS; i++) {
185 dev = DEVICE(&(s->adc[i]));
191 object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
186 sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
192 if (err != NULL) {
193 error_propagate(errp, err);
194 return;
195 }
196 busdev = SYS_BUS_DEVICE(dev);
197 sysbus_mmio_map(busdev, 0, adc_addr[i]);
198 sysbus_connect_irq(busdev, 0,
199 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
200 }
201
202 /* SPI devices */
203 for (i = 0; i < STM_NUM_SPIS; i++) {
204 dev = DEVICE(&(s->spi[i]));
187 if (err != NULL) {
188 error_propagate(errp, err);
189 return;
190 }
191 busdev = SYS_BUS_DEVICE(dev);
192 sysbus_mmio_map(busdev, 0, adc_addr[i]);
193 sysbus_connect_irq(busdev, 0,
194 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
195 }
196
197 /* SPI devices */
198 for (i = 0; i < STM_NUM_SPIS; i++) {
199 dev = DEVICE(&(s->spi[i]));
205 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
200 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
206 if (err != NULL) {
207 error_propagate(errp, err);
208 return;
209 }
210 busdev = SYS_BUS_DEVICE(dev);
211 sysbus_mmio_map(busdev, 0, spi_addr[i]);
212 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
213 }
214
215 /* EXTI device */
216 dev = DEVICE(&s->exti);
201 if (err != NULL) {
202 error_propagate(errp, err);
203 return;
204 }
205 busdev = SYS_BUS_DEVICE(dev);
206 sysbus_mmio_map(busdev, 0, spi_addr[i]);
207 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
208 }
209
210 /* EXTI device */
211 dev = DEVICE(&s->exti);
217 object_property_set_bool(OBJECT(&s->exti), true, "realized", &err);
212 sysbus_realize(SYS_BUS_DEVICE(&s->exti), &err);
218 if (err != NULL) {
219 error_propagate(errp, err);
220 return;
221 }
222 busdev = SYS_BUS_DEVICE(dev);
223 sysbus_mmio_map(busdev, 0, EXTI_ADDR);
224 for (i = 0; i < 16; i++) {
225 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));

--- 78 unchanged lines hidden --- 		213 if (err != NULL) {
214 error_propagate(errp, err);
215 return;
216 }
217 busdev = SYS_BUS_DEVICE(dev);
218 sysbus_mmio_map(busdev, 0, EXTI_ADDR);
219 for (i = 0; i < 16; i++) {
220 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));

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