stm32f205_soc.c (d649689a8ecb2e276cc20d3af6d416e3c299cb17) stm32f205_soc.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * STM32F205 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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46#define ADC_IRQ 18
47static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
48
49static void stm32f205_soc_initfn(Object *obj)
50{
51 STM32F205State *s = STM32F205_SOC(obj);
52 int i;
53
1/*
2 * STM32F205 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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46#define ADC_IRQ 18
47static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
48
49static void stm32f205_soc_initfn(Object *obj)
50{
51 STM32F205State *s = STM32F205_SOC(obj);
52 int i;
53
54 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
55 TYPE_ARMV7M);
54 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
56
55
57 sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
58 TYPE_STM32F2XX_SYSCFG);
56 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
59
60 for (i = 0; i < STM_NUM_USARTS; i++) {
57
58 for (i = 0; i < STM_NUM_USARTS; i++) {
61 sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
62 sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
59 object_initialize_child(obj, "usart[*]", &s->usart[i],
60 TYPE_STM32F2XX_USART);
63 }
64
65 for (i = 0; i < STM_NUM_TIMERS; i++) {
61 }
62
63 for (i = 0; i < STM_NUM_TIMERS; i++) {
66 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
67 sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
64 object_initialize_child(obj, "timer[*]", &s->timer[i],
65 TYPE_STM32F2XX_TIMER);
68 }
69
70 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
71
72 for (i = 0; i < STM_NUM_ADCS; i++) {
66 }
67
68 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
69
70 for (i = 0; i < STM_NUM_ADCS; i++) {
73 sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
74 TYPE_STM32F2XX_ADC);
71 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
75 }
76
77 for (i = 0; i < STM_NUM_SPIS; i++) {
72 }
73
74 for (i = 0; i < STM_NUM_SPIS; i++) {
78 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
79 TYPE_STM32F2XX_SPI);
75 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
80 }
81}
82
83static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
84{
85 STM32F205State *s = STM32F205_SOC(dev_soc);
86 DeviceState *dev, *armv7m;
87 SysBusDevice *busdev;

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106 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
107
108 armv7m = DEVICE(&s->armv7m);
109 qdev_prop_set_uint32(armv7m, "num-irq", 96);
110 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
111 qdev_prop_set_bit(armv7m, "enable-bitband", true);
112 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
113 "memory", &error_abort);
76 }
77}
78
79static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
80{
81 STM32F205State *s = STM32F205_SOC(dev_soc);
82 DeviceState *dev, *armv7m;
83 SysBusDevice *busdev;

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102 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
103
104 armv7m = DEVICE(&s->armv7m);
105 qdev_prop_set_uint32(armv7m, "num-irq", 96);
106 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
107 qdev_prop_set_bit(armv7m, "enable-bitband", true);
108 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
109 "memory", &error_abort);
114 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
110 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
115 if (err != NULL) {
116 error_propagate(errp, err);
117 return;
118 }
119
120 /* System configuration controller */
121 dev = DEVICE(&s->syscfg);
111 if (err != NULL) {
112 error_propagate(errp, err);
113 return;
114 }
115
116 /* System configuration controller */
117 dev = DEVICE(&s->syscfg);
122 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
118 sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
123 if (err != NULL) {
124 error_propagate(errp, err);
125 return;
126 }
127 busdev = SYS_BUS_DEVICE(dev);
128 sysbus_mmio_map(busdev, 0, 0x40013800);
129 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
130
131 /* Attach UART (uses USART registers) and USART controllers */
132 for (i = 0; i < STM_NUM_USARTS; i++) {
133 dev = DEVICE(&(s->usart[i]));
134 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
119 if (err != NULL) {
120 error_propagate(errp, err);
121 return;
122 }
123 busdev = SYS_BUS_DEVICE(dev);
124 sysbus_mmio_map(busdev, 0, 0x40013800);
125 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
126
127 /* Attach UART (uses USART registers) and USART controllers */
128 for (i = 0; i < STM_NUM_USARTS; i++) {
129 dev = DEVICE(&(s->usart[i]));
130 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
135 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
131 sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
136 if (err != NULL) {
137 error_propagate(errp, err);
138 return;
139 }
140 busdev = SYS_BUS_DEVICE(dev);
141 sysbus_mmio_map(busdev, 0, usart_addr[i]);
142 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
143 }
144
145 /* Timer 2 to 5 */
146 for (i = 0; i < STM_NUM_TIMERS; i++) {
147 dev = DEVICE(&(s->timer[i]));
148 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
132 if (err != NULL) {
133 error_propagate(errp, err);
134 return;
135 }
136 busdev = SYS_BUS_DEVICE(dev);
137 sysbus_mmio_map(busdev, 0, usart_addr[i]);
138 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
139 }
140
141 /* Timer 2 to 5 */
142 for (i = 0; i < STM_NUM_TIMERS; i++) {
143 dev = DEVICE(&(s->timer[i]));
144 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
149 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
145 sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
150 if (err != NULL) {
151 error_propagate(errp, err);
152 return;
153 }
154 busdev = SYS_BUS_DEVICE(dev);
155 sysbus_mmio_map(busdev, 0, timer_addr[i]);
156 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
157 }

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164 error_propagate(errp, err);
165 return;
166 }
167 qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
168 qdev_get_gpio_in(armv7m, ADC_IRQ));
169
170 for (i = 0; i < STM_NUM_ADCS; i++) {
171 dev = DEVICE(&(s->adc[i]));
146 if (err != NULL) {
147 error_propagate(errp, err);
148 return;
149 }
150 busdev = SYS_BUS_DEVICE(dev);
151 sysbus_mmio_map(busdev, 0, timer_addr[i]);
152 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
153 }

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160 error_propagate(errp, err);
161 return;
162 }
163 qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
164 qdev_get_gpio_in(armv7m, ADC_IRQ));
165
166 for (i = 0; i < STM_NUM_ADCS; i++) {
167 dev = DEVICE(&(s->adc[i]));
172 object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
168 sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
173 if (err != NULL) {
174 error_propagate(errp, err);
175 return;
176 }
177 busdev = SYS_BUS_DEVICE(dev);
178 sysbus_mmio_map(busdev, 0, adc_addr[i]);
179 sysbus_connect_irq(busdev, 0,
180 qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
181 }
182
183 /* SPI 1 and 2 */
184 for (i = 0; i < STM_NUM_SPIS; i++) {
185 dev = DEVICE(&(s->spi[i]));
169 if (err != NULL) {
170 error_propagate(errp, err);
171 return;
172 }
173 busdev = SYS_BUS_DEVICE(dev);
174 sysbus_mmio_map(busdev, 0, adc_addr[i]);
175 sysbus_connect_irq(busdev, 0,
176 qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
177 }
178
179 /* SPI 1 and 2 */
180 for (i = 0; i < STM_NUM_SPIS; i++) {
181 dev = DEVICE(&(s->spi[i]));
186 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
182 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
187 if (err != NULL) {
188 error_propagate(errp, err);
189 return;
190 }
191 busdev = SYS_BUS_DEVICE(dev);
192 sysbus_mmio_map(busdev, 0, spi_addr[i]);
193 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
194 }

--- 29 unchanged lines hidden --- 		183 if (err != NULL) {
184 error_propagate(errp, err);
185 return;
186 }
187 busdev = SYS_BUS_DEVICE(dev);
188 sysbus_mmio_map(busdev, 0, spi_addr[i]);
189 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
190 }

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