stm32f205_soc.c (a27bd6c779badb8d76e4430d810ef710a1b98f4e) stm32f205_soc.c (46517dd4971fc1fdd5b379e72cc377626ad98160)
1/*
2 * STM32F205 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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24
25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/module.h"
28#include "hw/arm/boot.h"
29#include "exec/address-spaces.h"
30#include "hw/arm/stm32f205_soc.h"
31#include "hw/qdev-properties.h"
1/*
2 * STM32F205 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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24
25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/module.h"
28#include "hw/arm/boot.h"
29#include "exec/address-spaces.h"
30#include "hw/arm/stm32f205_soc.h"
31#include "hw/qdev-properties.h"
32#include "sysemu/sysemu.h"
32
33/* At the moment only Timer 2 to 5 are modelled */
34static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
35 0x40000800, 0x40000C00 };
36static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
37 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
38static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
39 0x40012200 };

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34/* At the moment only Timer 2 to 5 are modelled */
35static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
36 0x40000800, 0x40000C00 };
37static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
38 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
39static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
40 0x40012200 };

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