omap_sx1.c (ef475b5dd12684591e6264e517eaa5b3e90f7ffa) omap_sx1.c (ba1ba5cca3962a9cc400c713c736b4fb8db1f38e)
1/* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2 *
3 * Copyright (C) 2008
4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
6 *
7 * based on PalmOne's (TM) PDAs support (palm.c)
8 */

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31#include "ui/console.h"
32#include "hw/arm/omap.h"
33#include "hw/boards.h"
34#include "hw/arm/arm.h"
35#include "hw/block/flash.h"
36#include "sysemu/block-backend.h"
37#include "sysemu/qtest.h"
38#include "exec/address-spaces.h"
1/* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2 *
3 * Copyright (C) 2008
4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
6 *
7 * based on PalmOne's (TM) PDAs support (palm.c)
8 */

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31#include "ui/console.h"
32#include "hw/arm/omap.h"
33#include "hw/boards.h"
34#include "hw/arm/arm.h"
35#include "hw/block/flash.h"
36#include "sysemu/block-backend.h"
37#include "sysemu/qtest.h"
38#include "exec/address-spaces.h"
39#include "cpu.h"
39
40/*****************************************************************************/
41/* Siemens SX1 Cellphone V1 */
42/* - ARM OMAP310 processor
43 * - SRAM 192 kB
44 * - SDRAM 32 MB at 0x10000000
45 * - Boot flash 16 MB at 0x00000000
46 * - Application flash 8 MB at 0x04000000

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115 uint32_t flash_size = flash0_size;
116 int be;
117
118 if (version == 2) {
119 flash_size = flash2_size;
120 }
121
122 mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
40
41/*****************************************************************************/
42/* Siemens SX1 Cellphone V1 */
43/* - ARM OMAP310 processor
44 * - SRAM 192 kB
45 * - SDRAM 32 MB at 0x10000000
46 * - Boot flash 16 MB at 0x00000000
47 * - Application flash 8 MB at 0x04000000

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116 uint32_t flash_size = flash0_size;
117 int be;
118
119 if (version == 2) {
120 flash_size = flash2_size;
121 }
122
123 mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
123 machine->cpu_model);
124 machine->cpu_type);
124
125 /* External Flash (EMIFS) */
126 memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
127 &error_fatal);
128 memory_region_set_readonly(flash, true);
129 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
130
131 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,

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219
220static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
221{
222 MachineClass *mc = MACHINE_CLASS(oc);
223
224 mc->desc = "Siemens SX1 (OMAP310) V2";
225 mc->init = sx1_init_v2;
226 mc->ignore_memory_transaction_failures = true;
125
126 /* External Flash (EMIFS) */
127 memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
128 &error_fatal);
129 memory_region_set_readonly(flash, true);
130 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
131
132 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,

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220
221static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
222{
223 MachineClass *mc = MACHINE_CLASS(oc);
224
225 mc->desc = "Siemens SX1 (OMAP310) V2";
226 mc->init = sx1_init_v2;
227 mc->ignore_memory_transaction_failures = true;
228 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
227}
228
229static const TypeInfo sx1_machine_v2_type = {
230 .name = MACHINE_TYPE_NAME("sx1"),
231 .parent = TYPE_MACHINE,
232 .class_init = sx1_machine_v2_class_init,
233};
234
235static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
236{
237 MachineClass *mc = MACHINE_CLASS(oc);
238
239 mc->desc = "Siemens SX1 (OMAP310) V1";
240 mc->init = sx1_init_v1;
241 mc->ignore_memory_transaction_failures = true;
229}
230
231static const TypeInfo sx1_machine_v2_type = {
232 .name = MACHINE_TYPE_NAME("sx1"),
233 .parent = TYPE_MACHINE,
234 .class_init = sx1_machine_v2_class_init,
235};
236
237static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
238{
239 MachineClass *mc = MACHINE_CLASS(oc);
240
241 mc->desc = "Siemens SX1 (OMAP310) V1";
242 mc->init = sx1_init_v1;
243 mc->ignore_memory_transaction_failures = true;
244 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
242}
243
244static const TypeInfo sx1_machine_v1_type = {
245 .name = MACHINE_TYPE_NAME("sx1-v1"),
246 .parent = TYPE_MACHINE,
247 .class_init = sx1_machine_v1_class_init,
248};
249
250static void sx1_machine_init(void)
251{
252 type_register_static(&sx1_machine_v1_type);
253 type_register_static(&sx1_machine_v2_type);
254}
255
256type_init(sx1_machine_init)
245}
246
247static const TypeInfo sx1_machine_v1_type = {
248 .name = MACHINE_TYPE_NAME("sx1-v1"),
249 .parent = TYPE_MACHINE,
250 .class_init = sx1_machine_v1_class_init,
251};
252
253static void sx1_machine_init(void)
254{
255 type_register_static(&sx1_machine_v1_type);
256 type_register_static(&sx1_machine_v2_type);
257}
258
259type_init(sx1_machine_init)