npcm7xx.c - OpenGrok cross reference for /openbmc/qemu/hw/arm/npcm7xx.c

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npcm7xx.c (7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42)	npcm7xx.c (326ccfe240ca9ef4f659a241b39390fa956e999b)
1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 30 unchanged lines hidden (view full) --- 39#define NPCM7XX_OTP2_BA (0xf018a000) 40 41/* Core system modules. */ 42#define NPCM7XX_L2C_BA (0xf03fc000) 43#define NPCM7XX_CPUP_BA (0xf03fe000) 44#define NPCM7XX_GCR_BA (0xf0800000) 45#define NPCM7XX_CLK_BA (0xf0801000) 46#define NPCM7XX_MC_BA (0xf0824000)	1/* 2 * Nuvoton NPCM7xx SoC family. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or --- 30 unchanged lines hidden (view full) --- 39#define NPCM7XX_OTP2_BA (0xf018a000) 40 41/* Core system modules. */ 42#define NPCM7XX_L2C_BA (0xf03fc000) 43#define NPCM7XX_CPUP_BA (0xf03fe000) 44#define NPCM7XX_GCR_BA (0xf0800000) 45#define NPCM7XX_CLK_BA (0xf0801000) 46#define NPCM7XX_MC_BA (0xf0824000)
	47#define NPCM7XX_RNG_BA (0xf000b000)
47 48/* Internal AHB SRAM / 49#define NPCM7XX_RAM3_BA (0xc0008000) 50#define NPCM7XX_RAM3_SZ (4 KiB) 51 52/* Memory blocks at the end of the address space / 53#define NPCM7XX_RAM2_BA (0xfffd0000) 54#define NPCM7XX_RAM2_SZ (128 KiB) --- 196 unchanged lines hidden (view full) --- 251 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 252 "power-on-straps"); 253 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 254 object_initialize_child(obj, "otp1", &s->key_storage, 255 TYPE_NPCM7XX_KEY_STORAGE); 256 object_initialize_child(obj, "otp2", &s->fuse_array, 257 TYPE_NPCM7XX_FUSE_ARRAY); 258 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);	48 49/* Internal AHB SRAM / 50#define NPCM7XX_RAM3_BA (0xc0008000) 51#define NPCM7XX_RAM3_SZ (4 KiB) 52 53/* Memory blocks at the end of the address space / 54#define NPCM7XX_RAM2_BA (0xfffd0000) 55#define NPCM7XX_RAM2_SZ (128 KiB) --- 196 unchanged lines hidden (view full) --- 252 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), 253 "power-on-straps"); 254 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); 255 object_initialize_child(obj, "otp1", &s->key_storage, 256 TYPE_NPCM7XX_KEY_STORAGE); 257 object_initialize_child(obj, "otp2", &s->fuse_array, 258 TYPE_NPCM7XX_FUSE_ARRAY); 259 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
	260 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
259 260 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 261 object_initialize_child(obj, "tim[]", &s->tim[i], TYPE_NPCM7XX_TIMER); 262 } 263 264 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 265 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 266 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], --- 102 unchanged lines hidden* (view full) --- 369 370 /* UART0..3 (16550 compatible) */ 371 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 372 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 373 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 374 serial_hd(i), DEVICE_LITTLE_ENDIAN); 375 } 376	261 262 for (i = 0; i < ARRAY_SIZE(s->tim); i++) { 263 object_initialize_child(obj, "tim[]", &s->tim[i], TYPE_NPCM7XX_TIMER); 264 } 265 266 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 267 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 268 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], --- 102 unchanged lines hidden* (view full) --- 371 372 /* UART0..3 (16550 compatible) */ 373 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { 374 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, 375 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, 376 serial_hd(i), DEVICE_LITTLE_ENDIAN); 377 } 378
	379 /* Random Number Generator. Cannot fail. */ 380 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); 381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); 382
377 /* 378 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 379 * specified, but this is a programming error. 380 / 381 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 382 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 383 SysBusDevice sbd = SYS_BUS_DEVICE(&s->fiu[i]); 384 int j; --- 22 unchanged lines hidden (view full) --- 407 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 408 &error_abort); 409 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 410 411 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 412 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 413 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 414 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);	383 /* 384 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects 385 * specified, but this is a programming error. 386 / 387 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); 388 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { 389 SysBusDevice sbd = SYS_BUS_DEVICE(&s->fiu[i]); 390 int j; --- 22 unchanged lines hidden (view full) --- 413 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, 414 &error_abort); 415 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); 416 417 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); 418 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); 419 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); 420 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
415 create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB);
416 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 417 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 418 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 419 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 420 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 421 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 422 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 423 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); --- 121 unchanged lines hidden ---	421 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); 422 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); 423 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); 424 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); 425 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); 426 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); 427 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); 428 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); --- 121 unchanged lines hidden ---