npcm7xx.c (2d2c73d0e3d504a61f868e46e6abd5643f38091b) npcm7xx.c (7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42)
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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81 NPCM7XX_TIMER7_IRQ,
82 NPCM7XX_TIMER8_IRQ,
83 NPCM7XX_TIMER9_IRQ,
84 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
85 NPCM7XX_TIMER11_IRQ,
86 NPCM7XX_TIMER12_IRQ,
87 NPCM7XX_TIMER13_IRQ,
88 NPCM7XX_TIMER14_IRQ,
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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81 NPCM7XX_TIMER7_IRQ,
82 NPCM7XX_TIMER8_IRQ,
83 NPCM7XX_TIMER9_IRQ,
84 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
85 NPCM7XX_TIMER11_IRQ,
86 NPCM7XX_TIMER12_IRQ,
87 NPCM7XX_TIMER13_IRQ,
88 NPCM7XX_TIMER14_IRQ,
89 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
90 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
91 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
89};
90
91/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
92#define NPCM7XX_NUM_IRQ (160)
93
94/* Register base address for each Timer Module */
95static const hwaddr npcm7xx_tim_addr[] = {
96 0xf0008000,

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348 sysbus_realize(sbd, &error_abort);
349 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
350
351 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
352 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
353 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
354 sysbus_connect_irq(sbd, j, irq);
355 }
92};
93
94/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
95#define NPCM7XX_NUM_IRQ (160)
96
97/* Register base address for each Timer Module */
98static const hwaddr npcm7xx_tim_addr[] = {
99 0xf0008000,

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351 sysbus_realize(sbd, &error_abort);
352 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
353
354 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
355 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
356 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
357 sysbus_connect_irq(sbd, j, irq);
358 }
359
360 /* IRQ for watchdogs */
361 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
362 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
363 /* GPIO that connects clk module with watchdog */
364 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
365 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
366 qdev_get_gpio_in_named(DEVICE(&s->clk),
367 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
356 }
357
358 /* UART0..3 (16550 compatible) */
359 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
360 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
361 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
362 serial_hd(i), DEVICE_LITTLE_ENDIAN);
363 }

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369
370 /* UART0..3 (16550 compatible) */
371 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
372 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
373 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
374 serial_hd(i), DEVICE_LITTLE_ENDIAN);
375 }

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