npcm7xx.c (1351f892467bd8d9655b43b8fbf10a8d08890612) npcm7xx.c (b821242c7b3b174bbf7c01a19c93c4e52fedab5d)
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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94/* Register base address for each 16550 UART */
95static const hwaddr npcm7xx_uart_addr[] = {
96 0xf0001000,
97 0xf0002000,
98 0xf0003000,
99 0xf0004000,
100};
101
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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94/* Register base address for each 16550 UART */
95static const hwaddr npcm7xx_uart_addr[] = {
96 0xf0001000,
97 0xf0002000,
98 0xf0003000,
99 0xf0004000,
100};
101
102/* Direct memory-mapped access to SPI0 CS0-1. */
103static const hwaddr npcm7xx_fiu0_flash_addr[] = {
104 0x80000000, /* CS0 */
105 0x88000000, /* CS1 */
106};
107
108/* Direct memory-mapped access to SPI3 CS0-3. */
109static const hwaddr npcm7xx_fiu3_flash_addr[] = {
110 0xa0000000, /* CS0 */
111 0xa8000000, /* CS1 */
112 0xb0000000, /* CS2 */
113 0xb8000000, /* CS3 */
114};
115
116static const struct {
117 const char *name;
118 hwaddr regs_addr;
119 int cs_count;
120 const hwaddr *flash_addr;
121} npcm7xx_fiu[] = {
122 {
123 .name = "fiu0",
124 .regs_addr = 0xfb000000,
125 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
126 .flash_addr = npcm7xx_fiu0_flash_addr,
127 }, {
128 .name = "fiu3",
129 .regs_addr = 0xc0000000,
130 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
131 .flash_addr = npcm7xx_fiu3_flash_addr,
132 },
133};
134
102static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
103 const struct arm_boot_info *info)
104{
105 /*
106 * The default smpboot stub halts the secondary CPU with a 'wfi'
107 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
108 * does not send an IPI to wake it up, so the second CPU fails to boot. So
109 * we need to provide our own smpboot stub that can not use 'wfi', it has

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187 TYPE_NPCM7XX_KEY_STORAGE);
188 object_initialize_child(obj, "otp2", &s->fuse_array,
189 TYPE_NPCM7XX_FUSE_ARRAY);
190 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
191
192 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
193 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
194 }
135static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
136 const struct arm_boot_info *info)
137{
138 /*
139 * The default smpboot stub halts the secondary CPU with a 'wfi'
140 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
141 * does not send an IPI to wake it up, so the second CPU fails to boot. So
142 * we need to provide our own smpboot stub that can not use 'wfi', it has

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220 TYPE_NPCM7XX_KEY_STORAGE);
221 object_initialize_child(obj, "otp2", &s->fuse_array,
222 TYPE_NPCM7XX_FUSE_ARRAY);
223 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
224
225 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
226 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
227 }
228
229 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
230 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
231 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
232 TYPE_NPCM7XX_FIU);
233 }
195}
196
197static void npcm7xx_realize(DeviceState *dev, Error **errp)
198{
199 NPCM7xxState *s = NPCM7XX(dev);
200 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
201 int i;
202

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286
287 /* UART0..3 (16550 compatible) */
288 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
289 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
290 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
291 serial_hd(i), DEVICE_LITTLE_ENDIAN);
292 }
293
234}
235
236static void npcm7xx_realize(DeviceState *dev, Error **errp)
237{
238 NPCM7xxState *s = NPCM7XX(dev);
239 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
240 int i;
241

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325
326 /* UART0..3 (16550 compatible) */
327 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
328 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
329 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
330 serial_hd(i), DEVICE_LITTLE_ENDIAN);
331 }
332
333 /*
334 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
335 * specified, but this is a programming error.
336 */
337 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
338 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
339 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
340 int j;
341
342 object_property_set_int(OBJECT(sbd), "cs-count",
343 npcm7xx_fiu[i].cs_count, &error_abort);
344 sysbus_realize(sbd, &error_abort);
345
346 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
347 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
348 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
349 }
350 }
351
294 /* RAM2 (SRAM) */
295 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
296 NPCM7XX_RAM2_SZ, &error_abort);
297 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
298
299 /* RAM3 (SRAM) */
300 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
301 NPCM7XX_RAM3_SZ, &error_abort);

--- 141 unchanged lines hidden --- 		352 /* RAM2 (SRAM) */
353 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
354 NPCM7XX_RAM2_SZ, &error_abort);
355 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
356
357 /* RAM3 (SRAM) */
358 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
359 NPCM7XX_RAM3_SZ, &error_abort);

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