npcm7xx.c (0be12dc76aabda6399a28d9b5e450da2bb94cb22) npcm7xx.c (77c05b0b746119a78bffb595b0313d39ac6b20fc)
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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46#define NPCM7XX_CLK_BA (0xf0801000)
47#define NPCM7XX_MC_BA (0xf0824000)
48#define NPCM7XX_RNG_BA (0xf000b000)
49
50/* USB Host modules */
51#define NPCM7XX_EHCI_BA (0xf0806000)
52#define NPCM7XX_OHCI_BA (0xf0807000)
53
1/*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or

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46#define NPCM7XX_CLK_BA (0xf0801000)
47#define NPCM7XX_MC_BA (0xf0824000)
48#define NPCM7XX_RNG_BA (0xf000b000)
49
50/* USB Host modules */
51#define NPCM7XX_EHCI_BA (0xf0806000)
52#define NPCM7XX_OHCI_BA (0xf0807000)
53
54/* ADC Module */
55#define NPCM7XX_ADC_BA (0xf000c000)
56
54/* Internal AHB SRAM */
55#define NPCM7XX_RAM3_BA (0xc0008000)
56#define NPCM7XX_RAM3_SZ (4 * KiB)
57
58/* Memory blocks at the end of the address space */
59#define NPCM7XX_RAM2_BA (0xfffd0000)
60#define NPCM7XX_RAM2_SZ (128 * KiB)
61#define NPCM7XX_ROM_BA (0xffff0000)
62#define NPCM7XX_ROM_SZ (64 * KiB)
63
57/* Internal AHB SRAM */
58#define NPCM7XX_RAM3_BA (0xc0008000)
59#define NPCM7XX_RAM3_SZ (4 * KiB)
60
61/* Memory blocks at the end of the address space */
62#define NPCM7XX_RAM2_BA (0xfffd0000)
63#define NPCM7XX_RAM2_SZ (128 * KiB)
64#define NPCM7XX_ROM_BA (0xffff0000)
65#define NPCM7XX_ROM_SZ (64 * KiB)
66
67
64/* Clock configuration values to be fixed up when bypassing bootloader */
65
66/* Run PLL1 at 1600 MHz */
67#define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
68/* Run the CPU from PLL1 and UART from PLL2 */
69#define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
70
71/*
72 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
73 * interrupts.
74 */
75enum NPCM7xxInterrupt {
68/* Clock configuration values to be fixed up when bypassing bootloader */
69
70/* Run PLL1 at 1600 MHz */
71#define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
72/* Run the CPU from PLL1 and UART from PLL2 */
73#define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
74
75/*
76 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
77 * interrupts.
78 */
79enum NPCM7xxInterrupt {
80 NPCM7XX_ADC_IRQ = 0,
76 NPCM7XX_UART0_IRQ = 2,
77 NPCM7XX_UART1_IRQ,
78 NPCM7XX_UART2_IRQ,
79 NPCM7XX_UART3_IRQ,
80 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
81 NPCM7XX_TIMER1_IRQ,
82 NPCM7XX_TIMER2_IRQ,
83 NPCM7XX_TIMER3_IRQ,

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291 * The initial mask of disabled modules indicates the chip derivative (e.g.
292 * NPCM750 or NPCM730).
293 */
294 value = tswap32(nc->disabled_modules);
295 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
296 sizeof(value));
297}
298
81 NPCM7XX_UART0_IRQ = 2,
82 NPCM7XX_UART1_IRQ,
83 NPCM7XX_UART2_IRQ,
84 NPCM7XX_UART3_IRQ,
85 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
86 NPCM7XX_TIMER1_IRQ,
87 NPCM7XX_TIMER2_IRQ,
88 NPCM7XX_TIMER3_IRQ,

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296 * The initial mask of disabled modules indicates the chip derivative (e.g.
297 * NPCM750 or NPCM730).
298 */
299 value = tswap32(nc->disabled_modules);
300 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
301 sizeof(value));
302}
303
304static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
305{
306 /* Both ADC and the fuse array must have realized. */
307 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
308 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
309 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
310}
311
299static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
300{
301 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
302}
303
304static void npcm7xx_init(Object *obj)
305{
306 NPCM7xxState *s = NPCM7XX(obj);

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317 "power-on-straps");
318 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
319 object_initialize_child(obj, "otp1", &s->key_storage,
320 TYPE_NPCM7XX_KEY_STORAGE);
321 object_initialize_child(obj, "otp2", &s->fuse_array,
322 TYPE_NPCM7XX_FUSE_ARRAY);
323 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
324 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
312static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
313{
314 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
315}
316
317static void npcm7xx_init(Object *obj)
318{
319 NPCM7xxState *s = NPCM7XX(obj);

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330 "power-on-straps");
331 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
332 object_initialize_child(obj, "otp1", &s->key_storage,
333 TYPE_NPCM7XX_KEY_STORAGE);
334 object_initialize_child(obj, "otp2", &s->fuse_array,
335 TYPE_NPCM7XX_FUSE_ARRAY);
336 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
337 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
338 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
325
326 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
327 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
328 }
329
330 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
331 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
332 }

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409 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
411 npcm7xx_init_fuses(s);
412
413 /* Fake Memory Controller (MC). Cannot fail. */
414 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
416
339
340 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
341 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
342 }
343
344 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
345 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
346 }

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423 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
425 npcm7xx_init_fuses(s);
426
427 /* Fake Memory Controller (MC). Cannot fail. */
428 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
430
431 /* ADC Modules. Cannot fail. */
432 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
433 DEVICE(&s->clk), "adc-clock"));
434 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
435 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
437 npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
438 npcm7xx_write_adc_calibration(s);
439
417 /* Timer Modules (TIM). Cannot fail. */
418 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
419 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
420 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
421 int first_irq;
422 int j;
423
424 /* Connect the timer clock. */

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523 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
524 &error_abort);
525 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
526
527 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
528 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
529 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
530 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
440 /* Timer Modules (TIM). Cannot fail. */
441 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
442 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
443 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
444 int first_irq;
445 int j;
446
447 /* Connect the timer clock. */

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546 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
547 &error_abort);
548 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
549
550 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
551 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
552 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
553 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
531 create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
532 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
533 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
534 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
535 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB);
536 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB);
537 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB);
538 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB);
539 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB);

--- 118 unchanged lines hidden --- 		554 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
555 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
556 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
557 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB);
558 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB);
559 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB);
560 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB);
561 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB);

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