msf2-soc.c (0db949f1810f4d497762d57d8db6f219c0607529) msf2-soc.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * SmartFusion2 SoC emulation.
3 *
4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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66 }
67}
68
69static void m2sxxx_soc_initfn(Object *obj)
70{
71 MSF2State *s = MSF2_SOC(obj);
72 int i;
73
1/*
2 * SmartFusion2 SoC emulation.
3 *
4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

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66 }
67}
68
69static void m2sxxx_soc_initfn(Object *obj)
70{
71 MSF2State *s = MSF2_SOC(obj);
72 int i;
73
74 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
75 TYPE_ARMV7M);
74 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
76
75
77 sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
78 TYPE_MSF2_SYSREG);
76 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
79
77
80 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
81 TYPE_MSS_TIMER);
78 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
82
83 for (i = 0; i < MSF2_NUM_SPIS; i++) {
79
80 for (i = 0; i < MSF2_NUM_SPIS; i++) {
84 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
85 TYPE_MSS_SPI);
81 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
86 }
87
82 }
83
88 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
89 TYPE_MSS_EMAC);
84 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
90 if (nd_table[0].used) {
91 qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
92 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
93 }
94}
95
96static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
97{

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125 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
126
127 armv7m = DEVICE(&s->armv7m);
128 qdev_prop_set_uint32(armv7m, "num-irq", 81);
129 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
130 qdev_prop_set_bit(armv7m, "enable-bitband", true);
131 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
132 "memory", &error_abort);
85 if (nd_table[0].used) {
86 qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
87 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
88 }
89}
90
91static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
92{

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120 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
121
122 armv7m = DEVICE(&s->armv7m);
123 qdev_prop_set_uint32(armv7m, "num-irq", 81);
124 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
125 qdev_prop_set_bit(armv7m, "enable-bitband", true);
126 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
127 "memory", &error_abort);
133 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
128 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
134 if (err != NULL) {
135 error_propagate(errp, err);
136 return;
137 }
138
139 if (!s->m3clk) {
140 error_setg(errp, "Invalid m3clk value");
141 error_append_hint(errp, "m3clk can not be zero\n");

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153 qdev_get_gpio_in(armv7m, uart_irq[i]),
154 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
155 }
156 }
157
158 dev = DEVICE(&s->timer);
159 /* APB0 clock is the timer input clock */
160 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
129 if (err != NULL) {
130 error_propagate(errp, err);
131 return;
132 }
133
134 if (!s->m3clk) {
135 error_setg(errp, "Invalid m3clk value");
136 error_append_hint(errp, "m3clk can not be zero\n");

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148 qdev_get_gpio_in(armv7m, uart_irq[i]),
149 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
150 }
151 }
152
153 dev = DEVICE(&s->timer);
154 /* APB0 clock is the timer input clock */
155 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
161 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
156 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
162 if (err != NULL) {
163 error_propagate(errp, err);
164 return;
165 }
166 busdev = SYS_BUS_DEVICE(dev);
167 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
168 sysbus_connect_irq(busdev, 0,
169 qdev_get_gpio_in(armv7m, timer_irq[0]));
170 sysbus_connect_irq(busdev, 1,
171 qdev_get_gpio_in(armv7m, timer_irq[1]));
172
173 dev = DEVICE(&s->sysreg);
174 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
175 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
157 if (err != NULL) {
158 error_propagate(errp, err);
159 return;
160 }
161 busdev = SYS_BUS_DEVICE(dev);
162 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
163 sysbus_connect_irq(busdev, 0,
164 qdev_get_gpio_in(armv7m, timer_irq[0]));
165 sysbus_connect_irq(busdev, 1,
166 qdev_get_gpio_in(armv7m, timer_irq[1]));
167
168 dev = DEVICE(&s->sysreg);
169 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
170 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
176 object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
171 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), &err);
177 if (err != NULL) {
178 error_propagate(errp, err);
179 return;
180 }
181 busdev = SYS_BUS_DEVICE(dev);
182 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
183
184 for (i = 0; i < MSF2_NUM_SPIS; i++) {
185 gchar *bus_name;
186
172 if (err != NULL) {
173 error_propagate(errp, err);
174 return;
175 }
176 busdev = SYS_BUS_DEVICE(dev);
177 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
178
179 for (i = 0; i < MSF2_NUM_SPIS; i++) {
180 gchar *bus_name;
181
187 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
182 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
188 if (err != NULL) {
189 error_propagate(errp, err);
190 return;
191 }
192
193 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
194 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
195 qdev_get_gpio_in(armv7m, spi_irq[i]));
196
197 /* Alias controller SPI bus to the SoC itself */
198 bus_name = g_strdup_printf("spi%d", i);
199 object_property_add_alias(OBJECT(s), bus_name,
200 OBJECT(&s->spi[i]), "spi");
201 g_free(bus_name);
202 }
203
204 dev = DEVICE(&s->emac);
205 object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
206 "ahb-bus", &error_abort);
183 if (err != NULL) {
184 error_propagate(errp, err);
185 return;
186 }
187
188 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
189 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
190 qdev_get_gpio_in(armv7m, spi_irq[i]));
191
192 /* Alias controller SPI bus to the SoC itself */
193 bus_name = g_strdup_printf("spi%d", i);
194 object_property_add_alias(OBJECT(s), bus_name,
195 OBJECT(&s->spi[i]), "spi");
196 g_free(bus_name);
197 }
198
199 dev = DEVICE(&s->emac);
200 object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
201 "ahb-bus", &error_abort);
207 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
202 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
208 if (err != NULL) {
209 error_propagate(errp, err);
210 return;
211 }
212 busdev = SYS_BUS_DEVICE(dev);
213 sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
214 sysbus_connect_irq(busdev, 0,
215 qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));

--- 54 unchanged lines hidden --- 		203 if (err != NULL) {
204 error_propagate(errp, err);
205 return;
206 }
207 busdev = SYS_BUS_DEVICE(dev);
208 sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
209 sysbus_connect_irq(busdev, 0,
210 qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));

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