mps2.c (d28e29a92585e94264628b1b27262fe2d7573f51) mps2.c (ba1ba5cca3962a9cc400c713c736b4fb8db1f38e)
1/*
2 * ARM V2M MPS2 board emulation.
3 *
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or

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41typedef enum MPS2FPGAType {
42 FPGA_AN385,
43 FPGA_AN511,
44} MPS2FPGAType;
45
46typedef struct {
47 MachineClass parent;
48 MPS2FPGAType fpga_type;
1/*
2 * ARM V2M MPS2 board emulation.
3 *
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or

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41typedef enum MPS2FPGAType {
42 FPGA_AN385,
43 FPGA_AN511,
44} MPS2FPGAType;
45
46typedef struct {
47 MachineClass parent;
48 MPS2FPGAType fpga_type;
49 const char *cpu_model;
50 uint32_t scc_id;
51} MPS2MachineClass;
52
53typedef struct {
54 MachineState parent;
55
56 ARMv7MState armv7m;
57 MemoryRegion psram;

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102 memory_region_add_subregion(get_system_memory(), base, mr);
103}
104
105static void mps2_common_init(MachineState *machine)
106{
107 MPS2MachineState *mms = MPS2_MACHINE(machine);
108 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
109 MemoryRegion *system_memory = get_system_memory();
49 uint32_t scc_id;
50} MPS2MachineClass;
51
52typedef struct {
53 MachineState parent;
54
55 ARMv7MState armv7m;
56 MemoryRegion psram;

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101 memory_region_add_subregion(get_system_memory(), base, mr);
102}
103
104static void mps2_common_init(MachineState *machine)
105{
106 MPS2MachineState *mms = MPS2_MACHINE(machine);
107 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
108 MemoryRegion *system_memory = get_system_memory();
109 MachineClass *mc = MACHINE_GET_CLASS(machine);
110 DeviceState *armv7m, *sccdev;
111
110 DeviceState *armv7m, *sccdev;
111
112 if (!machine->cpu_model) {
113 machine->cpu_model = mmc->cpu_model;
114 }
115
116 if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
117 error_report("This board can only be used with CPU %s", mmc->cpu_model);
112 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
113 error_report("This board can only be used with CPU %s",
114 mc->default_cpu_type);
118 exit(1);
119 }
120
121 /* The FPGA images have an odd combination of different RAMs,
122 * because in hardware they are different implementations and
123 * connected to different buses, giving varying performance/size
124 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
125 * call the 16MB our "system memory", as it's the largest lump.

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183 qdev_prop_set_uint32(armv7m, "num-irq", 32);
184 break;
185 case FPGA_AN511:
186 qdev_prop_set_uint32(armv7m, "num-irq", 64);
187 break;
188 default:
189 g_assert_not_reached();
190 }
115 exit(1);
116 }
117
118 /* The FPGA images have an odd combination of different RAMs,
119 * because in hardware they are different implementations and
120 * connected to different buses, giving varying performance/size
121 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
122 * call the 16MB our "system memory", as it's the largest lump.

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180 qdev_prop_set_uint32(armv7m, "num-irq", 32);
181 break;
182 case FPGA_AN511:
183 qdev_prop_set_uint32(armv7m, "num-irq", 64);
184 break;
185 default:
186 g_assert_not_reached();
187 }
191 qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
188 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
192 object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
193 "memory", &error_abort);
194 object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
195 &error_fatal);
196
197 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
198 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
199 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);

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334
335static void mps2_an385_class_init(ObjectClass *oc, void *data)
336{
337 MachineClass *mc = MACHINE_CLASS(oc);
338 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
339
340 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
341 mmc->fpga_type = FPGA_AN385;
189 object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
190 "memory", &error_abort);
191 object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
192 &error_fatal);
193
194 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
195 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
196 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);

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331
332static void mps2_an385_class_init(ObjectClass *oc, void *data)
333{
334 MachineClass *mc = MACHINE_CLASS(oc);
335 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
336
337 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
338 mmc->fpga_type = FPGA_AN385;
342 mmc->cpu_model = "cortex-m3";
339 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
343 mmc->scc_id = 0x41040000 | (385 << 4);
344}
345
346static void mps2_an511_class_init(ObjectClass *oc, void *data)
347{
348 MachineClass *mc = MACHINE_CLASS(oc);
349 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
350
351 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
352 mmc->fpga_type = FPGA_AN511;
340 mmc->scc_id = 0x41040000 | (385 << 4);
341}
342
343static void mps2_an511_class_init(ObjectClass *oc, void *data)
344{
345 MachineClass *mc = MACHINE_CLASS(oc);
346 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
347
348 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
349 mmc->fpga_type = FPGA_AN511;
353 mmc->cpu_model = "cortex-m3";
350 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
354 mmc->scc_id = 0x4104000 | (511 << 4);
355}
356
357static const TypeInfo mps2_info = {
358 .name = TYPE_MPS2_MACHINE,
359 .parent = TYPE_MACHINE,
360 .abstract = true,
361 .instance_size = sizeof(MPS2MachineState),

--- 24 unchanged lines hidden --- 		351 mmc->scc_id = 0x4104000 | (511 << 4);
352}
353
354static const TypeInfo mps2_info = {
355 .name = TYPE_MPS2_MACHINE,
356 .parent = TYPE_MACHINE,
357 .abstract = true,
358 .instance_size = sizeof(MPS2MachineState),

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