fsl-imx7.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) fsl-imx7.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * i.MX7 SoC definitions
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * Based on hw/arm/fsl-imx6.c

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40 snprintf(name, NAME_SIZE, "cpu%d", i);
41 object_initialize_child(obj, name, &s->cpu[i],
42 ARM_CPU_TYPE_NAME("cortex-a7"));
43 }
44
45 /*
46 * A7MPCORE
47 */
1/*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * i.MX7 SoC definitions
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * Based on hw/arm/fsl-imx6.c

--- 31 unchanged lines hidden (view full) ---

40 snprintf(name, NAME_SIZE, "cpu%d", i);
41 object_initialize_child(obj, name, &s->cpu[i],
42 ARM_CPU_TYPE_NAME("cortex-a7"));
43 }
44
45 /*
46 * A7MPCORE
47 */
48 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
49 TYPE_A15MPCORE_PRIV);
48 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
49 TYPE_A15MPCORE_PRIV);
50
51 /*
52 * GPIOs 1 to 7
53 */
54 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
55 snprintf(name, NAME_SIZE, "gpio%d", i);
50
51 /*
52 * GPIOs 1 to 7
53 */
54 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
55 snprintf(name, NAME_SIZE, "gpio%d", i);
56 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
57 TYPE_IMX_GPIO);
56 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
58 }
59
60 /*
61 * GPT1, 2, 3, 4
62 */
63 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
64 snprintf(name, NAME_SIZE, "gpt%d", i);
57 }
58
59 /*
60 * GPT1, 2, 3, 4
61 */
62 for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
63 snprintf(name, NAME_SIZE, "gpt%d", i);
65 sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
66 TYPE_IMX7_GPT);
64 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
67 }
68
69 /*
70 * CCM
71 */
65 }
66
67 /*
68 * CCM
69 */
72 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
70 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
73
74 /*
75 * Analog
76 */
71
72 /*
73 * Analog
74 */
77 sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog),
78 TYPE_IMX7_ANALOG);
75 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
79
80 /*
81 * GPCv2
82 */
76
77 /*
78 * GPCv2
79 */
83 sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
84 TYPE_IMX_GPCV2);
80 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
85
86 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
87 snprintf(name, NAME_SIZE, "spi%d", i + 1);
81
82 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
83 snprintf(name, NAME_SIZE, "spi%d", i + 1);
88 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
89 TYPE_IMX_SPI);
84 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
90 }
91
92
93 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
94 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
85 }
86
87
88 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
89 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
95 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
96 TYPE_IMX_I2C);
90 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
97 }
98
99 /*
100 * UART
101 */
102 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
103 snprintf(name, NAME_SIZE, "uart%d", i);
91 }
92
93 /*
94 * UART
95 */
96 for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
97 snprintf(name, NAME_SIZE, "uart%d", i);
104 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
105 TYPE_IMX_SERIAL);
98 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
106 }
107
108 /*
109 * Ethernet
110 */
111 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
112 snprintf(name, NAME_SIZE, "eth%d", i);
99 }
100
101 /*
102 * Ethernet
103 */
104 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
105 snprintf(name, NAME_SIZE, "eth%d", i);
113 sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
114 TYPE_IMX_ENET);
106 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
115 }
116
117 /*
118 * SDHCI
119 */
120 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
121 snprintf(name, NAME_SIZE, "usdhc%d", i);
107 }
108
109 /*
110 * SDHCI
111 */
112 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
113 snprintf(name, NAME_SIZE, "usdhc%d", i);
122 sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
123 TYPE_IMX_USDHC);
114 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
124 }
125
126 /*
127 * SNVS
128 */
115 }
116
117 /*
118 * SNVS
119 */
129 sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
130 TYPE_IMX7_SNVS);
120 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
131
132 /*
133 * Watchdog
134 */
135 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
136 snprintf(name, NAME_SIZE, "wdt%d", i);
121
122 /*
123 * Watchdog
124 */
125 for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
126 snprintf(name, NAME_SIZE, "wdt%d", i);
137 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
138 TYPE_IMX2_WDT);
127 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
139 }
140
141 /*
142 * GPR
143 */
128 }
129
130 /*
131 * GPR
132 */
144 sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
133 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
145
134
146 sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie),
147 TYPE_DESIGNWARE_PCIE_HOST);
135 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
148
149 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
150 snprintf(name, NAME_SIZE, "usb%d", i);
136
137 for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
138 snprintf(name, NAME_SIZE, "usb%d", i);
151 sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
152 TYPE_CHIPIDEA);
139 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
153 }
154}
155
156static void fsl_imx7_realize(DeviceState *dev, Error **errp)
157{
158 MachineState *ms = MACHINE(qdev_get_machine());
159 FslIMX7State *s = FSL_IMX7(dev);
160 Object *o;

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194 * A7MPCORE
195 */
196 object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
197 &error_abort);
198 object_property_set_int(OBJECT(&s->a7mpcore),
199 FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
200 "num-irq", &error_abort);
201
140 }
141}
142
143static void fsl_imx7_realize(DeviceState *dev, Error **errp)
144{
145 MachineState *ms = MACHINE(qdev_get_machine());
146 FslIMX7State *s = FSL_IMX7(dev);
147 Object *o;

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181 * A7MPCORE
182 */
183 object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
184 &error_abort);
185 object_property_set_int(OBJECT(&s->a7mpcore),
186 FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
187 "num-irq", &error_abort);
188
202 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
203 &error_abort);
189 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
205
206 for (i = 0; i < smp_cpus; i++) {
207 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
208 DeviceState *d = DEVICE(qemu_get_cpu(i));
209
210 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
211 sysbus_connect_irq(sbd, i, irq);

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230 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
231 FSL_IMX7_GPT1_ADDR,
232 FSL_IMX7_GPT2_ADDR,
233 FSL_IMX7_GPT3_ADDR,
234 FSL_IMX7_GPT4_ADDR,
235 };
236
237 s->gpt[i].ccm = IMX_CCM(&s->ccm);
190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
191
192 for (i = 0; i < smp_cpus; i++) {
193 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
194 DeviceState *d = DEVICE(qemu_get_cpu(i));
195
196 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
197 sysbus_connect_irq(sbd, i, irq);

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216 static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
217 FSL_IMX7_GPT1_ADDR,
218 FSL_IMX7_GPT2_ADDR,
219 FSL_IMX7_GPT3_ADDR,
220 FSL_IMX7_GPT4_ADDR,
221 };
222
223 s->gpt[i].ccm = IMX_CCM(&s->ccm);
238 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
239 &error_abort);
224 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
240 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
241 }
242
243 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
244 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
245 FSL_IMX7_GPIO1_ADDR,
246 FSL_IMX7_GPIO2_ADDR,
247 FSL_IMX7_GPIO3_ADDR,
248 FSL_IMX7_GPIO4_ADDR,
249 FSL_IMX7_GPIO5_ADDR,
250 FSL_IMX7_GPIO6_ADDR,
251 FSL_IMX7_GPIO7_ADDR,
252 };
253
225 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
226 }
227
228 for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
229 static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
230 FSL_IMX7_GPIO1_ADDR,
231 FSL_IMX7_GPIO2_ADDR,
232 FSL_IMX7_GPIO3_ADDR,
233 FSL_IMX7_GPIO4_ADDR,
234 FSL_IMX7_GPIO5_ADDR,
235 FSL_IMX7_GPIO6_ADDR,
236 FSL_IMX7_GPIO7_ADDR,
237 };
238
254 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
255 &error_abort);
239 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
256 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
257 }
258
259 /*
260 * IOMUXC and IOMUXC_LPSR
261 */
262 for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
263 static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {

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268 snprintf(name, NAME_SIZE, "iomuxc%d", i);
269 create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
270 FSL_IMX7_IOMUXCn_SIZE);
271 }
272
273 /*
274 * CCM
275 */
240 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
241 }
242
243 /*
244 * IOMUXC and IOMUXC_LPSR
245 */
246 for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
247 static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {

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252 snprintf(name, NAME_SIZE, "iomuxc%d", i);
253 create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
254 FSL_IMX7_IOMUXCn_SIZE);
255 }
256
257 /*
258 * CCM
259 */
276 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
260 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
278
279 /*
280 * Analog
281 */
261 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
262
263 /*
264 * Analog
265 */
282 object_property_set_bool(OBJECT(&s->analog), true, "realized",
283 &error_abort);
266 sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
284 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
285
286 /*
287 * GPCv2
288 */
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
268
269 /*
270 * GPCv2
271 */
289 object_property_set_bool(OBJECT(&s->gpcv2), true,
290 "realized", &error_abort);
272 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
292
293 /* Initialize all ECSPI */
294 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
295 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
296 FSL_IMX7_ECSPI1_ADDR,
297 FSL_IMX7_ECSPI2_ADDR,
298 FSL_IMX7_ECSPI3_ADDR,
299 FSL_IMX7_ECSPI4_ADDR,
300 };
301
302 static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
303 FSL_IMX7_ECSPI1_IRQ,
304 FSL_IMX7_ECSPI2_IRQ,
305 FSL_IMX7_ECSPI3_IRQ,
306 FSL_IMX7_ECSPI4_IRQ,
307 };
308
309 /* Initialize the SPI */
273 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
274
275 /* Initialize all ECSPI */
276 for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
277 static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
278 FSL_IMX7_ECSPI1_ADDR,
279 FSL_IMX7_ECSPI2_ADDR,
280 FSL_IMX7_ECSPI3_ADDR,
281 FSL_IMX7_ECSPI4_ADDR,
282 };
283
284 static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
285 FSL_IMX7_ECSPI1_IRQ,
286 FSL_IMX7_ECSPI2_IRQ,
287 FSL_IMX7_ECSPI3_IRQ,
288 FSL_IMX7_ECSPI4_IRQ,
289 };
290
291 /* Initialize the SPI */
310 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
311 &error_abort);
292 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
313 FSL_IMX7_SPIn_ADDR[i]);
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
315 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
316 FSL_IMX7_SPIn_IRQ[i]));
317 }
318
319 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {

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326
327 static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
328 FSL_IMX7_I2C1_IRQ,
329 FSL_IMX7_I2C2_IRQ,
330 FSL_IMX7_I2C3_IRQ,
331 FSL_IMX7_I2C4_IRQ,
332 };
333
293 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
294 FSL_IMX7_SPIn_ADDR[i]);
295 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
296 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
297 FSL_IMX7_SPIn_IRQ[i]));
298 }
299
300 for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {

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307
308 static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
309 FSL_IMX7_I2C1_IRQ,
310 FSL_IMX7_I2C2_IRQ,
311 FSL_IMX7_I2C3_IRQ,
312 FSL_IMX7_I2C4_IRQ,
313 };
314
334 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
335 &error_abort);
315 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
337
338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
339 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
340 FSL_IMX7_I2Cn_IRQ[i]));
341 }
342
343 /*

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362 FSL_IMX7_UART5_IRQ,
363 FSL_IMX7_UART6_IRQ,
364 FSL_IMX7_UART7_IRQ,
365 };
366
367
368 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
369
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
317
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
319 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
320 FSL_IMX7_I2Cn_IRQ[i]));
321 }
322
323 /*

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342 FSL_IMX7_UART5_IRQ,
343 FSL_IMX7_UART6_IRQ,
344 FSL_IMX7_UART7_IRQ,
345 };
346
347
348 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
349
370 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
371 &error_abort);
350 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
372
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
374
375 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
377 }
378
379 /*
380 * Ethernet
381 */
382 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
383 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
384 FSL_IMX7_ENET1_ADDR,
385 FSL_IMX7_ENET2_ADDR,
386 };
387
388 object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
389 "tx-ring-num", &error_abort);
390 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
351
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
353
354 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
356 }
357
358 /*
359 * Ethernet
360 */
361 for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
362 static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
363 FSL_IMX7_ENET1_ADDR,
364 FSL_IMX7_ENET2_ADDR,
365 };
366
367 object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
368 "tx-ring-num", &error_abort);
369 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
391 object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
392 &error_abort);
370 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
393
394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
395
396 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
398 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
399 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
400 }

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410 };
411
412 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
413 FSL_IMX7_USDHC1_IRQ,
414 FSL_IMX7_USDHC2_IRQ,
415 FSL_IMX7_USDHC3_IRQ,
416 };
417
371
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
373
374 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
375 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
376 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
378 }

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388 };
389
390 static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
391 FSL_IMX7_USDHC1_IRQ,
392 FSL_IMX7_USDHC2_IRQ,
393 FSL_IMX7_USDHC3_IRQ,
394 };
395
418 object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
419 &error_abort);
396 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
420
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
422 FSL_IMX7_USDHCn_ADDR[i]);
423
424 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
426 }
427
428 /*
429 * SNVS
430 */
397
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
399 FSL_IMX7_USDHCn_ADDR[i]);
400
401 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
403 }
404
405 /*
406 * SNVS
407 */
431 object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
408 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
433
434 /*
435 * SRC
436 */
437 create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
438
439 /*

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450 FSL_IMX7_WDOG1_IRQ,
451 FSL_IMX7_WDOG2_IRQ,
452 FSL_IMX7_WDOG3_IRQ,
453 FSL_IMX7_WDOG4_IRQ,
454 };
455
456 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
457 &error_abort);
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
410
411 /*
412 * SRC
413 */
414 create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
415
416 /*

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427 FSL_IMX7_WDOG1_IRQ,
428 FSL_IMX7_WDOG2_IRQ,
429 FSL_IMX7_WDOG3_IRQ,
430 FSL_IMX7_WDOG4_IRQ,
431 };
432
433 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
434 &error_abort);
458 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
459 &error_abort);
435 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
460
461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
462 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
463 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
464 FSL_IMX7_WDOGn_IRQ[i]));
465 }
466
467 /*

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489 create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
490
491 /*
492 * OCOTP
493 */
494 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
495 FSL_IMX7_OCOTP_SIZE);
496
436
437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
439 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
440 FSL_IMX7_WDOGn_IRQ[i]));
441 }
442
443 /*

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465 create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
466
467 /*
468 * OCOTP
469 */
470 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
471 FSL_IMX7_OCOTP_SIZE);
472
497 object_property_set_bool(OBJECT(&s->gpr), true, "realized",
498 &error_abort);
473 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
499 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
500
474 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
475
501 object_property_set_bool(OBJECT(&s->pcie), true,
502 "realized", &error_abort);
476 sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
503 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
504
505 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
507 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
509 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);

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526 };
527
528 static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
529 FSL_IMX7_USB1_IRQ,
530 FSL_IMX7_USB2_IRQ,
531 FSL_IMX7_USB3_IRQ,
532 };
533
477 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
478
479 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
481 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
483 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);

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500 };
501
502 static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
503 FSL_IMX7_USB1_IRQ,
504 FSL_IMX7_USB2_IRQ,
505 FSL_IMX7_USB3_IRQ,
506 };
507
534 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
535 &error_abort);
508 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
537 FSL_IMX7_USBn_ADDR[i]);
538
539 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
540 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
541
542 snprintf(name, NAME_SIZE, "usbmisc%d", i);
543 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],

--- 59 unchanged lines hidden --- 		509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
510 FSL_IMX7_USBn_ADDR[i]);
511
512 irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
514
515 snprintf(name, NAME_SIZE, "usbmisc%d", i);
516 create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],

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