fsl-imx6ul.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) fsl-imx6ul.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6UL SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx7.c
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 26 unchanged lines hidden (view full) ---

35 int i;
36
37 object_initialize_child(obj, "cpu0", &s->cpu,
38 ARM_CPU_TYPE_NAME("cortex-a7"));
39
40 /*
41 * A7MPCORE
42 */
1/*
2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6UL SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx7.c
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 26 unchanged lines hidden (view full) ---

35 int i;
36
37 object_initialize_child(obj, "cpu0", &s->cpu,
38 ARM_CPU_TYPE_NAME("cortex-a7"));
39
40 /*
41 * A7MPCORE
42 */
43 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
44 TYPE_A15MPCORE_PRIV);
43 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
44 TYPE_A15MPCORE_PRIV);
45
46 /*
47 * CCM
48 */
45
46 /*
47 * CCM
48 */
49 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
49 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
50
51 /*
52 * SRC
53 */
50
51 /*
52 * SRC
53 */
54 sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
55
56 /*
57 * GPCv2
58 */
55
56 /*
57 * GPCv2
58 */
59 sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
60 TYPE_IMX_GPCV2);
59 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
61
62 /*
63 * SNVS
64 */
60
61 /*
62 * SNVS
63 */
65 sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
66 TYPE_IMX7_SNVS);
64 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
67
68 /*
69 * GPR
70 */
65
66 /*
67 * GPR
68 */
71 sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
72 TYPE_IMX7_GPR);
69 object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
73
74 /*
75 * GPIOs 1 to 5
76 */
77 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
78 snprintf(name, NAME_SIZE, "gpio%d", i);
70
71 /*
72 * GPIOs 1 to 5
73 */
74 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
75 snprintf(name, NAME_SIZE, "gpio%d", i);
79 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
80 TYPE_IMX_GPIO);
76 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
81 }
82
83 /*
84 * GPT 1, 2
85 */
86 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
87 snprintf(name, NAME_SIZE, "gpt%d", i);
77 }
78
79 /*
80 * GPT 1, 2
81 */
82 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
83 snprintf(name, NAME_SIZE, "gpt%d", i);
88 sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
89 TYPE_IMX7_GPT);
84 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
90 }
91
92 /*
93 * EPIT 1, 2
94 */
95 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
96 snprintf(name, NAME_SIZE, "epit%d", i + 1);
85 }
86
87 /*
88 * EPIT 1, 2
89 */
90 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
91 snprintf(name, NAME_SIZE, "epit%d", i + 1);
97 sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
98 TYPE_IMX_EPIT);
92 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
99 }
100
101 /*
102 * eCSPI
103 */
104 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
105 snprintf(name, NAME_SIZE, "spi%d", i + 1);
93 }
94
95 /*
96 * eCSPI
97 */
98 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
99 snprintf(name, NAME_SIZE, "spi%d", i + 1);
106 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
107 TYPE_IMX_SPI);
100 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
108 }
109
110 /*
111 * I2C
112 */
113 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
114 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
101 }
102
103 /*
104 * I2C
105 */
106 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
107 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
115 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
116 TYPE_IMX_I2C);
108 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
117 }
118
119 /*
120 * UART
121 */
122 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
123 snprintf(name, NAME_SIZE, "uart%d", i);
109 }
110
111 /*
112 * UART
113 */
114 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
115 snprintf(name, NAME_SIZE, "uart%d", i);
124 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
125 TYPE_IMX_SERIAL);
116 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
126 }
127
128 /*
129 * Ethernet
130 */
131 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
132 snprintf(name, NAME_SIZE, "eth%d", i);
117 }
118
119 /*
120 * Ethernet
121 */
122 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
123 snprintf(name, NAME_SIZE, "eth%d", i);
133 sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
134 TYPE_IMX_ENET);
124 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
135 }
136
137 /* USB */
138 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
139 snprintf(name, NAME_SIZE, "usbphy%d", i);
125 }
126
127 /* USB */
128 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
129 snprintf(name, NAME_SIZE, "usbphy%d", i);
140 sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
141 TYPE_IMX_USBPHY);
130 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
142 }
143 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
144 snprintf(name, NAME_SIZE, "usb%d", i);
131 }
132 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
133 snprintf(name, NAME_SIZE, "usb%d", i);
145 sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
146 TYPE_CHIPIDEA);
134 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
147 }
148
149 /*
150 * SDHCI
151 */
152 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
153 snprintf(name, NAME_SIZE, "usdhc%d", i);
135 }
136
137 /*
138 * SDHCI
139 */
140 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
141 snprintf(name, NAME_SIZE, "usdhc%d", i);
154 sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
155 TYPE_IMX_USDHC);
142 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
156 }
157
158 /*
159 * Watchdog
160 */
161 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
162 snprintf(name, NAME_SIZE, "wdt%d", i);
143 }
144
145 /*
146 * Watchdog
147 */
148 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
149 snprintf(name, NAME_SIZE, "wdt%d", i);
163 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
164 TYPE_IMX2_WDT);
150 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
165 }
166}
167
168static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
169{
170 MachineState *ms = MACHINE(qdev_get_machine());
171 FslIMX6ULState *s = FSL_IMX6UL(dev);
172 int i;

--- 14 unchanged lines hidden (view full) ---

187
188 /*
189 * A7MPCORE
190 */
191 object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort);
192 object_property_set_int(OBJECT(&s->a7mpcore),
193 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
194 "num-irq", &error_abort);
151 }
152}
153
154static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
155{
156 MachineState *ms = MACHINE(qdev_get_machine());
157 FslIMX6ULState *s = FSL_IMX6UL(dev);
158 int i;

--- 14 unchanged lines hidden (view full) ---

173
174 /*
175 * A7MPCORE
176 */
177 object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort);
178 object_property_set_int(OBJECT(&s->a7mpcore),
179 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
180 "num-irq", &error_abort);
195 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
196 &error_abort);
181 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
197 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
198
199 sbd = SYS_BUS_DEVICE(&s->a7mpcore);
200 d = DEVICE(&s->cpu);
201
202 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
203 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
204 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));

--- 15 unchanged lines hidden (view full) ---

220 };
221
222 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
223 FSL_IMX6UL_GPT1_IRQ,
224 FSL_IMX6UL_GPT2_IRQ,
225 };
226
227 s->gpt[i].ccm = IMX_CCM(&s->ccm);
182 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
183
184 sbd = SYS_BUS_DEVICE(&s->a7mpcore);
185 d = DEVICE(&s->cpu);
186
187 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
188 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
189 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));

--- 15 unchanged lines hidden (view full) ---

205 };
206
207 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
208 FSL_IMX6UL_GPT1_IRQ,
209 FSL_IMX6UL_GPT2_IRQ,
210 };
211
212 s->gpt[i].ccm = IMX_CCM(&s->ccm);
228 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
229 &error_abort);
213 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
230
231 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
232 FSL_IMX6UL_GPTn_ADDR[i]);
233
234 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
235 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
236 FSL_IMX6UL_GPTn_IRQ[i]));
237 }

--- 8 unchanged lines hidden (view full) ---

246 };
247
248 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
249 FSL_IMX6UL_EPIT1_IRQ,
250 FSL_IMX6UL_EPIT2_IRQ,
251 };
252
253 s->epit[i].ccm = IMX_CCM(&s->ccm);
214
215 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
216 FSL_IMX6UL_GPTn_ADDR[i]);
217
218 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
219 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
220 FSL_IMX6UL_GPTn_IRQ[i]));
221 }

--- 8 unchanged lines hidden (view full) ---

230 };
231
232 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
233 FSL_IMX6UL_EPIT1_IRQ,
234 FSL_IMX6UL_EPIT2_IRQ,
235 };
236
237 s->epit[i].ccm = IMX_CCM(&s->ccm);
254 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
255 &error_abort);
238 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
256
257 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
258 FSL_IMX6UL_EPITn_ADDR[i]);
259
260 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
261 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
262 FSL_IMX6UL_EPITn_IRQ[i]));
263 }

--- 21 unchanged lines hidden (view full) ---

285 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
286 FSL_IMX6UL_GPIO1_HIGH_IRQ,
287 FSL_IMX6UL_GPIO2_HIGH_IRQ,
288 FSL_IMX6UL_GPIO3_HIGH_IRQ,
289 FSL_IMX6UL_GPIO4_HIGH_IRQ,
290 FSL_IMX6UL_GPIO5_HIGH_IRQ,
291 };
292
239
240 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
241 FSL_IMX6UL_EPITn_ADDR[i]);
242
243 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
244 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
245 FSL_IMX6UL_EPITn_IRQ[i]));
246 }

--- 21 unchanged lines hidden (view full) ---

268 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
269 FSL_IMX6UL_GPIO1_HIGH_IRQ,
270 FSL_IMX6UL_GPIO2_HIGH_IRQ,
271 FSL_IMX6UL_GPIO3_HIGH_IRQ,
272 FSL_IMX6UL_GPIO4_HIGH_IRQ,
273 FSL_IMX6UL_GPIO5_HIGH_IRQ,
274 };
275
293 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
294 &error_abort);
276 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
295
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
297 FSL_IMX6UL_GPIOn_ADDR[i]);
298
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
300 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
301 FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
302

--- 13 unchanged lines hidden (view full) ---

316
317 snprintf(name, NAME_SIZE, "iomuxc%d", i);
318 create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
319 }
320
321 /*
322 * CCM
323 */
277
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
279 FSL_IMX6UL_GPIOn_ADDR[i]);
280
281 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
282 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
283 FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
284

--- 13 unchanged lines hidden (view full) ---

298
299 snprintf(name, NAME_SIZE, "iomuxc%d", i);
300 create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
301 }
302
303 /*
304 * CCM
305 */
324 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
306 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
326
327 /*
328 * SRC
329 */
307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
308
309 /*
310 * SRC
311 */
330 object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
312 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
332
333 /*
334 * GPCv2
335 */
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
314
315 /*
316 * GPCv2
317 */
336 object_property_set_bool(OBJECT(&s->gpcv2), true,
337 "realized", &error_abort);
318 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
339
340 /* Initialize all ECSPI */
341 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
342 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
343 FSL_IMX6UL_ECSPI1_ADDR,
344 FSL_IMX6UL_ECSPI2_ADDR,
345 FSL_IMX6UL_ECSPI3_ADDR,
346 FSL_IMX6UL_ECSPI4_ADDR,
347 };
348
349 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
350 FSL_IMX6UL_ECSPI1_IRQ,
351 FSL_IMX6UL_ECSPI2_IRQ,
352 FSL_IMX6UL_ECSPI3_IRQ,
353 FSL_IMX6UL_ECSPI4_IRQ,
354 };
355
356 /* Initialize the SPI */
319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
320
321 /* Initialize all ECSPI */
322 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
323 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
324 FSL_IMX6UL_ECSPI1_ADDR,
325 FSL_IMX6UL_ECSPI2_ADDR,
326 FSL_IMX6UL_ECSPI3_ADDR,
327 FSL_IMX6UL_ECSPI4_ADDR,
328 };
329
330 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
331 FSL_IMX6UL_ECSPI1_IRQ,
332 FSL_IMX6UL_ECSPI2_IRQ,
333 FSL_IMX6UL_ECSPI3_IRQ,
334 FSL_IMX6UL_ECSPI4_IRQ,
335 };
336
337 /* Initialize the SPI */
357 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
358 &error_abort);
338 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
359
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
361 FSL_IMX6UL_SPIn_ADDR[i]);
362
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
364 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
365 FSL_IMX6UL_SPIn_IRQ[i]));
366 }

--- 11 unchanged lines hidden (view full) ---

378
379 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
380 FSL_IMX6UL_I2C1_IRQ,
381 FSL_IMX6UL_I2C2_IRQ,
382 FSL_IMX6UL_I2C3_IRQ,
383 FSL_IMX6UL_I2C4_IRQ,
384 };
385
339
340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
341 FSL_IMX6UL_SPIn_ADDR[i]);
342
343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
344 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
345 FSL_IMX6UL_SPIn_IRQ[i]));
346 }

--- 11 unchanged lines hidden (view full) ---

358
359 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
360 FSL_IMX6UL_I2C1_IRQ,
361 FSL_IMX6UL_I2C2_IRQ,
362 FSL_IMX6UL_I2C3_IRQ,
363 FSL_IMX6UL_I2C4_IRQ,
364 };
365
386 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
387 &error_abort);
366 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
389
390 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
391 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
392 FSL_IMX6UL_I2Cn_IRQ[i]));
393 }
394
395 /*

--- 19 unchanged lines hidden (view full) ---

415 FSL_IMX6UL_UART5_IRQ,
416 FSL_IMX6UL_UART6_IRQ,
417 FSL_IMX6UL_UART7_IRQ,
418 FSL_IMX6UL_UART8_IRQ,
419 };
420
421 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
422
367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
368
369 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
370 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
371 FSL_IMX6UL_I2Cn_IRQ[i]));
372 }
373
374 /*

--- 19 unchanged lines hidden (view full) ---

394 FSL_IMX6UL_UART5_IRQ,
395 FSL_IMX6UL_UART6_IRQ,
396 FSL_IMX6UL_UART7_IRQ,
397 FSL_IMX6UL_UART8_IRQ,
398 };
399
400 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
401
423 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
424 &error_abort);
402 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
425
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
427 FSL_IMX6UL_UARTn_ADDR[i]);
428
429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
430 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
431 FSL_IMX6UL_UARTn_IRQ[i]));
432 }

--- 16 unchanged lines hidden (view full) ---

449 FSL_IMX6UL_ENET1_TIMER_IRQ,
450 FSL_IMX6UL_ENET2_TIMER_IRQ,
451 };
452
453 object_property_set_uint(OBJECT(&s->eth[i]),
454 FSL_IMX6UL_ETH_NUM_TX_RINGS,
455 "tx-ring-num", &error_abort);
456 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
403
404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
405 FSL_IMX6UL_UARTn_ADDR[i]);
406
407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
408 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
409 FSL_IMX6UL_UARTn_IRQ[i]));
410 }

--- 16 unchanged lines hidden (view full) ---

427 FSL_IMX6UL_ENET1_TIMER_IRQ,
428 FSL_IMX6UL_ENET2_TIMER_IRQ,
429 };
430
431 object_property_set_uint(OBJECT(&s->eth[i]),
432 FSL_IMX6UL_ETH_NUM_TX_RINGS,
433 "tx-ring-num", &error_abort);
434 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
457 object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
458 &error_abort);
435 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
459
460 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
461 FSL_IMX6UL_ENETn_ADDR[i]);
462
463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
464 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
465 FSL_IMX6UL_ENETn_IRQ[i]));
466
467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
468 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
469 FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
470 }
471
472 /* USB */
473 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
436
437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
438 FSL_IMX6UL_ENETn_ADDR[i]);
439
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
441 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
442 FSL_IMX6UL_ENETn_IRQ[i]));
443
444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
445 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
446 FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
447 }
448
449 /* USB */
450 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
474 object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
475 &error_abort);
451 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
476 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
477 FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
478 }
479
480 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
481 static const int FSL_IMX6UL_USBn_IRQ[] = {
482 FSL_IMX6UL_USB1_IRQ,
483 FSL_IMX6UL_USB2_IRQ,
484 };
452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
453 FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
454 }
455
456 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
457 static const int FSL_IMX6UL_USBn_IRQ[] = {
458 FSL_IMX6UL_USB1_IRQ,
459 FSL_IMX6UL_USB2_IRQ,
460 };
485 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
486 &error_abort);
461 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
487 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
488 FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
490 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
491 FSL_IMX6UL_USBn_IRQ[i]));
492 }
493
494 /*

--- 5 unchanged lines hidden (view full) ---

500 FSL_IMX6UL_USDHC2_ADDR,
501 };
502
503 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
504 FSL_IMX6UL_USDHC1_IRQ,
505 FSL_IMX6UL_USDHC2_IRQ,
506 };
507
462 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
463 FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
465 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
466 FSL_IMX6UL_USBn_IRQ[i]));
467 }
468
469 /*

--- 5 unchanged lines hidden (view full) ---

475 FSL_IMX6UL_USDHC2_ADDR,
476 };
477
478 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
479 FSL_IMX6UL_USDHC1_IRQ,
480 FSL_IMX6UL_USDHC2_IRQ,
481 };
482
508 object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
509 &error_abort);
483 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
510
511 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
512 FSL_IMX6UL_USDHCn_ADDR[i]);
513
514 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
515 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
516 FSL_IMX6UL_USDHCn_IRQ[i]));
517 }
518
519 /*
520 * SNVS
521 */
484
485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
486 FSL_IMX6UL_USDHCn_ADDR[i]);
487
488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
489 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
490 FSL_IMX6UL_USDHCn_IRQ[i]));
491 }
492
493 /*
494 * SNVS
495 */
522 object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
496 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
523 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
524
525 /*
526 * Watchdog
527 */
528 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
529 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
530 FSL_IMX6UL_WDOG1_ADDR,
531 FSL_IMX6UL_WDOG2_ADDR,
532 FSL_IMX6UL_WDOG3_ADDR,
533 };
534 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
535 FSL_IMX6UL_WDOG1_IRQ,
536 FSL_IMX6UL_WDOG2_IRQ,
537 FSL_IMX6UL_WDOG3_IRQ,
538 };
539
540 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
541 &error_abort);
497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
498
499 /*
500 * Watchdog
501 */
502 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
503 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
504 FSL_IMX6UL_WDOG1_ADDR,
505 FSL_IMX6UL_WDOG2_ADDR,
506 FSL_IMX6UL_WDOG3_ADDR,
507 };
508 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
509 FSL_IMX6UL_WDOG1_IRQ,
510 FSL_IMX6UL_WDOG2_IRQ,
511 FSL_IMX6UL_WDOG3_IRQ,
512 };
513
514 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
515 &error_abort);
542 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
543 &error_abort);
516 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
544
545 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
546 FSL_IMX6UL_WDOGn_ADDR[i]);
547 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
548 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
549 FSL_IMX6UL_WDOGn_IRQ[i]));
550 }
551
552 /*
553 * GPR
554 */
517
518 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
519 FSL_IMX6UL_WDOGn_ADDR[i]);
520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
521 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
522 FSL_IMX6UL_WDOGn_IRQ[i]));
523 }
524
525 /*
526 * GPR
527 */
555 object_property_set_bool(OBJECT(&s->gpr), true, "realized",
556 &error_abort);
528 sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
557 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
558
559 /*
560 * SDMA
561 */
562 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
563
564 /*

--- 95 unchanged lines hidden --- 		529 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
530
531 /*
532 * SDMA
533 */
534 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
535
536 /*

--- 95 unchanged lines hidden ---