fsl-imx31.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) fsl-imx31.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX31 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 21 unchanged lines hidden (view full) ---

30
31static void fsl_imx31_init(Object *obj)
32{
33 FslIMX31State *s = FSL_IMX31(obj);
34 int i;
35
36 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
37
1/*
2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX31 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 21 unchanged lines hidden (view full) ---

30
31static void fsl_imx31_init(Object *obj)
32{
33 FslIMX31State *s = FSL_IMX31(obj);
34 int i;
35
36 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136"));
37
38 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
39 TYPE_IMX_AVIC);
38 object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
40
39
41 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
40 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX31_CCM);
42
43 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
41
42 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
44 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
45 TYPE_IMX_SERIAL);
43 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
46 }
47
44 }
45
48 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
46 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX31_GPT);
49
50 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
47
48 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
51 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
52 TYPE_IMX_EPIT);
49 object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
53 }
54
55 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
50 }
51
52 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
56 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
57 TYPE_IMX_I2C);
53 object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
58 }
59
60 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
54 }
55
56 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
61 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
62 TYPE_IMX_GPIO);
57 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
63 }
64
58 }
59
65 sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT);
60 object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
66}
67
68static void fsl_imx31_realize(DeviceState *dev, Error **errp)
69{
70 FslIMX31State *s = FSL_IMX31(dev);
71 uint16_t i;
72 Error *err = NULL;
73
74 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
75 if (err) {
76 error_propagate(errp, err);
77 return;
78 }
79
61}
62
63static void fsl_imx31_realize(DeviceState *dev, Error **errp)
64{
65 FslIMX31State *s = FSL_IMX31(dev);
66 uint16_t i;
67 Error *err = NULL;
68
69 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
70 if (err) {
71 error_propagate(errp, err);
72 return;
73 }
74
80 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
75 sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
81 if (err) {
82 error_propagate(errp, err);
83 return;
84 }
85 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
86 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
87 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
88 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
89 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
90
76 if (err) {
77 error_propagate(errp, err);
78 return;
79 }
80 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
81 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
82 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
83 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
84 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
85
91 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
86 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
92 if (err) {
93 error_propagate(errp, err);
94 return;
95 }
96 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
97
98 /* Initialize all UARTS */
99 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
100 static const struct {
101 hwaddr addr;
102 unsigned int irq;
103 } serial_table[FSL_IMX31_NUM_UARTS] = {
104 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
105 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
106 };
107
108 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
109
87 if (err) {
88 error_propagate(errp, err);
89 return;
90 }
91 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
92
93 /* Initialize all UARTS */
94 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
95 static const struct {
96 hwaddr addr;
97 unsigned int irq;
98 } serial_table[FSL_IMX31_NUM_UARTS] = {
99 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
100 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
101 };
102
103 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
104
110 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
105 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
111 if (err) {
112 error_propagate(errp, err);
113 return;
114 }
115
116 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
117 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
118 qdev_get_gpio_in(DEVICE(&s->avic),
119 serial_table[i].irq));
120 }
121
122 s->gpt.ccm = IMX_CCM(&s->ccm);
123
106 if (err) {
107 error_propagate(errp, err);
108 return;
109 }
110
111 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
112 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
113 qdev_get_gpio_in(DEVICE(&s->avic),
114 serial_table[i].irq));
115 }
116
117 s->gpt.ccm = IMX_CCM(&s->ccm);
118
124 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
119 sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
125 if (err) {
126 error_propagate(errp, err);
127 return;
128 }
129
130 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
131 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
132 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));

--- 5 unchanged lines hidden (view full) ---

138 unsigned int irq;
139 } epit_table[FSL_IMX31_NUM_EPITS] = {
140 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
141 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
142 };
143
144 s->epit[i].ccm = IMX_CCM(&s->ccm);
145
120 if (err) {
121 error_propagate(errp, err);
122 return;
123 }
124
125 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
126 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
127 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));

--- 5 unchanged lines hidden (view full) ---

133 unsigned int irq;
134 } epit_table[FSL_IMX31_NUM_EPITS] = {
135 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
136 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
137 };
138
139 s->epit[i].ccm = IMX_CCM(&s->ccm);
140
146 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
141 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
147 if (err) {
148 error_propagate(errp, err);
149 return;
150 }
151
152 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
153 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
154 qdev_get_gpio_in(DEVICE(&s->avic),

--- 7 unchanged lines hidden (view full) ---

162 unsigned int irq;
163 } i2c_table[FSL_IMX31_NUM_I2CS] = {
164 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
165 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
166 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
167 };
168
169 /* Initialize the I2C */
142 if (err) {
143 error_propagate(errp, err);
144 return;
145 }
146
147 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
148 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
149 qdev_get_gpio_in(DEVICE(&s->avic),

--- 7 unchanged lines hidden (view full) ---

157 unsigned int irq;
158 } i2c_table[FSL_IMX31_NUM_I2CS] = {
159 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
160 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
161 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
162 };
163
164 /* Initialize the I2C */
170 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
165 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
171 if (err) {
172 error_propagate(errp, err);
173 return;
174 }
175 /* Map I2C memory */
176 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
177 /* Connect I2C IRQ to PIC */
178 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,

--- 9 unchanged lines hidden (view full) ---

188 } gpio_table[FSL_IMX31_NUM_GPIOS] = {
189 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
190 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
191 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
192 };
193
194 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
195 &error_abort);
166 if (err) {
167 error_propagate(errp, err);
168 return;
169 }
170 /* Map I2C memory */
171 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
172 /* Connect I2C IRQ to PIC */
173 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,

--- 9 unchanged lines hidden (view full) ---

183 } gpio_table[FSL_IMX31_NUM_GPIOS] = {
184 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
185 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
186 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
187 };
188
189 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
190 &error_abort);
196 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
191 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
197 if (err) {
198 error_propagate(errp, err);
199 return;
200 }
201 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
202 /* Connect GPIO IRQ to PIC */
203 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
204 qdev_get_gpio_in(DEVICE(&s->avic),
205 gpio_table[i].irq));
206 }
207
208 /* Watchdog */
192 if (err) {
193 error_propagate(errp, err);
194 return;
195 }
196 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
197 /* Connect GPIO IRQ to PIC */
198 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
199 qdev_get_gpio_in(DEVICE(&s->avic),
200 gpio_table[i].irq));
201 }
202
203 /* Watchdog */
209 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort);
204 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
210 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
211
212 /* On a real system, the first 16k is a `secure boot rom' */
213 memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
214 FSL_IMX31_SECURE_ROM_SIZE, &err);
215 if (err) {
216 error_propagate(errp, err);
217 return;

--- 58 unchanged lines hidden --- 		205 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR);
206
207 /* On a real system, the first 16k is a `secure boot rom' */
208 memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
209 FSL_IMX31_SECURE_ROM_SIZE, &err);
210 if (err) {
211 error_propagate(errp, err);
212 return;

--- 58 unchanged lines hidden ---