armsse.c (c89cef3a2cdfb355258890db8cfd2175add5bbee) armsse.c (446587a914cfa57c2ce529056a9ca2215bde7111)
1/*
2 * Arm SSE (Subsystems for Embedded): IoTKit
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or

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25#include "hw/qdev-clock.h"
26
27struct ARMSSEInfo {
28 const char *name;
29 uint32_t sse_version;
30 int sram_banks;
31 int num_cpus;
32 uint32_t sys_version;
1/*
2 * Arm SSE (Subsystems for Embedded): IoTKit
3 *
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or

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25#include "hw/qdev-clock.h"
26
27struct ARMSSEInfo {
28 const char *name;
29 uint32_t sse_version;
30 int sram_banks;
31 int num_cpus;
32 uint32_t sys_version;
33 uint32_t iidr;
33 uint32_t cpuwait_rst;
34 bool has_mhus;
35 bool has_ppus;
36 bool has_cachectrl;
37 bool has_cpusecctrl;
38 bool has_cpuid;
39 Property *props;
40};

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65
66static const ARMSSEInfo armsse_variants[] = {
67 {
68 .name = TYPE_IOTKIT,
69 .sse_version = ARMSSE_IOTKIT,
70 .sram_banks = 1,
71 .num_cpus = 1,
72 .sys_version = 0x41743,
34 uint32_t cpuwait_rst;
35 bool has_mhus;
36 bool has_ppus;
37 bool has_cachectrl;
38 bool has_cpusecctrl;
39 bool has_cpuid;
40 Property *props;
41};

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66
67static const ARMSSEInfo armsse_variants[] = {
68 {
69 .name = TYPE_IOTKIT,
70 .sse_version = ARMSSE_IOTKIT,
71 .sram_banks = 1,
72 .num_cpus = 1,
73 .sys_version = 0x41743,
74 .iidr = 0,
73 .cpuwait_rst = 0,
74 .has_mhus = false,
75 .has_ppus = false,
76 .has_cachectrl = false,
77 .has_cpusecctrl = false,
78 .has_cpuid = false,
79 .props = iotkit_properties,
80 },
81 {
82 .name = TYPE_SSE200,
83 .sse_version = ARMSSE_SSE200,
84 .sram_banks = 4,
85 .num_cpus = 2,
86 .sys_version = 0x22041743,
75 .cpuwait_rst = 0,
76 .has_mhus = false,
77 .has_ppus = false,
78 .has_cachectrl = false,
79 .has_cpusecctrl = false,
80 .has_cpuid = false,
81 .props = iotkit_properties,
82 },
83 {
84 .name = TYPE_SSE200,
85 .sse_version = ARMSSE_SSE200,
86 .sram_banks = 4,
87 .num_cpus = 2,
88 .sys_version = 0x22041743,
89 .iidr = 0,
87 .cpuwait_rst = 2,
88 .has_mhus = true,
89 .has_ppus = true,
90 .has_cachectrl = true,
91 .has_cpusecctrl = true,
92 .has_cpuid = true,
93 .props = armsse_properties,
94 },

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945 return;
946 }
947 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG",
948 armsse_sys_config_value(s, info), errp)) {
949 return;
950 }
951 object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
952 info->sse_version, &error_abort);
90 .cpuwait_rst = 2,
91 .has_mhus = true,
92 .has_ppus = true,
93 .has_cachectrl = true,
94 .has_cpusecctrl = true,
95 .has_cpuid = true,
96 .props = armsse_properties,
97 },

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948 return;
949 }
950 if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG",
951 armsse_sys_config_value(s, info), errp)) {
952 return;
953 }
954 object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
955 info->sse_version, &error_abort);
956 object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
957 info->iidr, &error_abort);
953 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) {
954 return;
955 }
956 /* System information registers */
957 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
958 /* System control registers */
959 object_property_set_int(OBJECT(&s->sysctl), "sse-version",
960 info->sse_version, &error_abort);

--- 254 unchanged lines hidden --- 		958 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) {
959 return;
960 }
961 /* System information registers */
962 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
963 /* System control registers */
964 object_property_set_int(OBJECT(&s->sysctl), "sse-version",
965 info->sse_version, &error_abort);

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