allwinner-h3.c (9fc7fc4d3909817555ce0af6bcb69dff1606140d) allwinner-h3.c (db873cc5d1a4aaa67eea87768d504b2f89d88738)
1/*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or

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193
194 s->memmap = allwinner_h3_memmap;
195
196 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
197 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
198 ARM_CPU_TYPE_NAME("cortex-a7"));
199 }
200
1/*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or

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193
194 s->memmap = allwinner_h3_memmap;
195
196 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
197 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
198 ARM_CPU_TYPE_NAME("cortex-a7"));
199 }
200
201 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
202 TYPE_ARM_GIC);
201 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
203
202
204 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
205 TYPE_AW_A10_PIT);
203 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
206 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
207 "clk0-freq");
208 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
209 "clk1-freq");
210
204 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
205 "clk0-freq");
206 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
207 "clk1-freq");
208
211 sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
212 TYPE_AW_H3_CCU);
209 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
213
210
214 sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
215 TYPE_AW_H3_SYSCTRL);
211 object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
216
212
217 sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
218 TYPE_AW_CPUCFG);
213 object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
219
214
220 sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
221 TYPE_AW_SID);
215 object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
222 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
223 "identifier");
224
216 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
217 "identifier");
218
225 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
226 TYPE_AW_SDHOST_SUN5I);
219 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
227
220
228 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
229 TYPE_AW_SUN8I_EMAC);
221 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
230
222
231 sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
232 TYPE_AW_H3_DRAMC);
223 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
233 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
234 "ram-addr");
235 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
236 "ram-size");
237
224 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
225 "ram-addr");
226 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
227 "ram-size");
228
238 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
239 TYPE_AW_RTC_SUN6I);
229 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
240}
241
242static void allwinner_h3_realize(DeviceState *dev, Error **errp)
243{
244 AwH3State *s = AW_H3(dev);
245 unsigned i;
246
247 /* CPUs */

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265
266 /* Generic Interrupt Controller */
267 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
268 GIC_INTERNAL);
269 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
270 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
271 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
230}
231
232static void allwinner_h3_realize(DeviceState *dev, Error **errp)
233{
234 AwH3State *s = AW_H3(dev);
235 unsigned i;
236
237 /* CPUs */

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255
256 /* Generic Interrupt Controller */
257 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
258 GIC_INTERNAL);
259 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
260 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
261 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
262 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
273 qdev_init_nofail(DEVICE(&s->gic));
263 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
274
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
279
280 /*
281 * Wire the outputs from each CPU's generic timer and the GICv3

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316
317 /* GIC maintenance signal */
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
319 qdev_get_gpio_in(DEVICE(&s->gic),
320 ppibase + AW_H3_GIC_PPI_MAINT));
321 }
322
323 /* Timer */
264
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
269
270 /*
271 * Wire the outputs from each CPU's generic timer and the GICv3

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306
307 /* GIC maintenance signal */
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
309 qdev_get_gpio_in(DEVICE(&s->gic),
310 ppibase + AW_H3_GIC_PPI_MAINT));
311 }
312
313 /* Timer */
324 qdev_init_nofail(DEVICE(&s->timer));
314 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
327 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
329 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
330
331 /* SRAM */
332 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",

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338 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
339 &s->sram_a1);
340 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
341 &s->sram_a2);
342 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
343 &s->sram_c);
344
345 /* Clock Control Unit */
315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
317 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
319 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
320
321 /* SRAM */
322 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",

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328 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
329 &s->sram_a1);
330 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
331 &s->sram_a2);
332 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
333 &s->sram_c);
334
335 /* Clock Control Unit */
346 qdev_init_nofail(DEVICE(&s->ccu));
336 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
348
349 /* System Control */
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
338
339 /* System Control */
350 qdev_init_nofail(DEVICE(&s->sysctrl));
340 sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
352
353 /* CPU Configuration */
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
342
343 /* CPU Configuration */
354 qdev_init_nofail(DEVICE(&s->cpucfg));
344 sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
356
357 /* Security Identifier */
345 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
346
347 /* Security Identifier */
358 qdev_init_nofail(DEVICE(&s->sid));
348 sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
360
361 /* SD/MMC */
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
350
351 /* SD/MMC */
362 qdev_init_nofail(DEVICE(&s->mmc0));
352 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
363 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
365 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
366
367 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
368 "sd-bus");
369
370 /* EMAC */
371 if (nd_table[0].used) {
372 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
373 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
374 }
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
355 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
356
357 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
358 "sd-bus");
359
360 /* EMAC */
361 if (nd_table[0].used) {
362 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
363 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
364 }
375 qdev_init_nofail(DEVICE(&s->emac));
365 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
378 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
379
380 /* Universal Serial Bus */
381 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
382 qdev_get_gpio_in(DEVICE(&s->gic),
383 AW_H3_GIC_SPI_EHCI0));

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417 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
418 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
419 /* UART3 */
420 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
421 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
422 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
423
424 /* DRAMC */
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
368 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
369
370 /* Universal Serial Bus */
371 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
372 qdev_get_gpio_in(DEVICE(&s->gic),
373 AW_H3_GIC_SPI_EHCI0));

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407 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
408 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
409 /* UART3 */
410 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
411 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
412 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
413
414 /* DRAMC */
425 qdev_init_nofail(DEVICE(&s->dramc));
415 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
429
430 /* RTC */
416 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
417 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
419
420 /* RTC */
431 qdev_init_nofail(DEVICE(&s->rtc));
421 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
433
434 /* Unimplemented devices */
435 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
436 create_unimplemented_device(unimplemented[i].device_name,
437 unimplemented[i].base,
438 unimplemented[i].size);
439 }

--- 25 unchanged lines hidden --- 		422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
423
424 /* Unimplemented devices */
425 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
426 create_unimplemented_device(unimplemented[i].device_name,
427 unimplemented[i].base,
428 unimplemented[i].size);
429 }

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