cputlb.c (e74c0cfa57323e5806894c65086f411112168820) cputlb.c (f52bfb12143e29d7c8bd827bdb751aee47a9694e)
1/*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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689 tn.addr_write = address | TLB_MMIO;
690 } else if (memory_region_is_ram(section->mr)
691 && cpu_physical_memory_is_clean(
692 memory_region_get_ram_addr(section->mr) + xlat)) {
693 tn.addr_write = address | TLB_NOTDIRTY;
694 } else {
695 tn.addr_write = address;
696 }
1/*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 680 unchanged lines hidden (view full) ---

689 tn.addr_write = address | TLB_MMIO;
690 } else if (memory_region_is_ram(section->mr)
691 && cpu_physical_memory_is_clean(
692 memory_region_get_ram_addr(section->mr) + xlat)) {
693 tn.addr_write = address | TLB_NOTDIRTY;
694 } else {
695 tn.addr_write = address;
696 }
697 if (prot & PAGE_WRITE_INV) {
698 tn.addr_write |= TLB_INVALID_MASK;
699 }
697 }
698
699 /* Pairs with flag setting in tlb_reset_dirty_range */
700 copy_tlb_helper(te, &tn, true);
701 /* atomic_mb_set(&te->addr_write, write_address); */
702}
703
704/* Add a new TLB entry, but without specifying the memory

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973 }
974
975 /* Check TLB entry and enforce page permissions. */
976 if ((addr & TARGET_PAGE_MASK)
977 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
978 if (!VICTIM_TLB_HIT(addr_write, addr)) {
979 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
980 }
700 }
701
702 /* Pairs with flag setting in tlb_reset_dirty_range */
703 copy_tlb_helper(te, &tn, true);
704 /* atomic_mb_set(&te->addr_write, write_address); */
705}
706
707/* Add a new TLB entry, but without specifying the memory

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976 }
977
978 /* Check TLB entry and enforce page permissions. */
979 if ((addr & TARGET_PAGE_MASK)
980 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
981 if (!VICTIM_TLB_HIT(addr_write, addr)) {
982 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
983 }
981 tlb_addr = tlbe->addr_write;
984 tlb_addr = tlbe->addr_write & ~TLB_INVALID_MASK;
982 }
983
984 /* Check notdirty */
985 if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
986 tlb_set_dirty(ENV_GET_CPU(env), addr);
987 tlb_addr = tlb_addr & ~TLB_NOTDIRTY;
988 }
989

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986
987 /* Check notdirty */
988 if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
989 tlb_set_dirty(ENV_GET_CPU(env), addr);
990 tlb_addr = tlb_addr & ~TLB_NOTDIRTY;
991 }
992

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