cputlb.c (50b107c5d617eaf93301cef20221312e7a986701) cputlb.c (03a981893c99faba84bb373976796ad7dce0aecc)
1/*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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1081 * Otherwise the function will return, and there will be a valid
1082 * entry in the TLB for this access.
1083 */
1084void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
1085 uintptr_t retaddr)
1086{
1087 uintptr_t index = tlb_index(env, mmu_idx, addr);
1088 CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
1/*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

--- 1072 unchanged lines hidden (view full) ---

1081 * Otherwise the function will return, and there will be a valid
1082 * entry in the TLB for this access.
1083 */
1084void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
1085 uintptr_t retaddr)
1086{
1087 uintptr_t index = tlb_index(env, mmu_idx, addr);
1088 CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
1089 target_ulong tlb_addr = tlb_addr_write(entry);
1089
1090
1090 if (!tlb_hit(tlb_addr_write(entry), addr)) {
1091 /* TLB entry is for a different page */
1091 if (unlikely(!tlb_hit(tlb_addr, addr))) {
1092 if (!VICTIM_TLB_HIT(addr_write, addr)) {
1093 tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
1094 mmu_idx, retaddr);
1092 if (!VICTIM_TLB_HIT(addr_write, addr)) {
1093 tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
1094 mmu_idx, retaddr);
1095 /* TLB resize via tlb_fill may have moved the entry. */
1096 index = tlb_index(env, mmu_idx, addr);
1097 entry = tlb_entry(env, mmu_idx, addr);
1095 }
1098 }
1099 tlb_addr = tlb_addr_write(entry);
1096 }
1100 }
1101
1102 /* Handle watchpoints. */
1103 if ((tlb_addr & TLB_WATCHPOINT) && size > 0) {
1104 cpu_check_watchpoint(env_cpu(env), addr, size,
1105 env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
1106 BP_MEM_WRITE, retaddr);
1107 }
1097}
1098
1099void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
1100 MMUAccessType access_type, int mmu_idx)
1101{
1102 CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
1103 uintptr_t tlb_addr, page;
1104 size_t elt_ofs;

--- 716 unchanged lines hidden --- 		1108}
1109
1110void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
1111 MMUAccessType access_type, int mmu_idx)
1112{
1113 CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
1114 uintptr_t tlb_addr, page;
1115 size_t elt_ofs;

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