turbostat.c (e651262477c6d8cba79dffc1a6039da43d9c96b0) turbostat.c (0f7887c49b0c454aef9936a6eadabe1c91b5af55)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 1708 unchanged lines hidden (view full) ---

1717 ratio = (msr >> 0) & 0xFF;
1718 if (ratio)
1719 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n",
1720 ratio, bclk, ratio * bclk);
1721 return;
1722}
1723
1724static void
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 1708 unchanged lines hidden (view full) ---

1717 ratio = (msr >> 0) & 0xFF;
1718 if (ratio)
1719 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n",
1720 ratio, bclk, ratio * bclk);
1721 return;
1722}
1723
1724static void
1725dump_atom_turbo_ratio_limits(void)
1726{
1727 unsigned long long msr;
1728 unsigned int ratio;
1729
1730 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
1731 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1732
1733 ratio = (msr >> 0) & 0x3F;
1734 if (ratio)
1735 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
1736 ratio, bclk, ratio * bclk);
1737
1738 ratio = (msr >> 8) & 0x3F;
1739 if (ratio)
1740 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
1741 ratio, bclk, ratio * bclk);
1742
1743 ratio = (msr >> 16) & 0x3F;
1744 if (ratio)
1745 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1746 ratio, bclk, ratio * bclk);
1747
1748 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
1749 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1750
1751 ratio = (msr >> 24) & 0x3F;
1752 if (ratio)
1753 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1754 ratio, bclk, ratio * bclk);
1755
1756 ratio = (msr >> 16) & 0x3F;
1757 if (ratio)
1758 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1759 ratio, bclk, ratio * bclk);
1760
1761 ratio = (msr >> 8) & 0x3F;
1762 if (ratio)
1763 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1764 ratio, bclk, ratio * bclk);
1765
1766 ratio = (msr >> 0) & 0x3F;
1767 if (ratio)
1768 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
1769 ratio, bclk, ratio * bclk);
1770}
1771
1772static void
1725dump_knl_turbo_ratio_limits(void)
1726{
1727 const unsigned int buckets_no = 7;
1728
1729 unsigned long long msr;
1730 int delta_cores, delta_ratio;
1731 int i, b_nr;
1732 unsigned int cores[buckets_no];

--- 758 unchanged lines hidden (view full) ---

2491
2492 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2493 base_ratio = (msr >> 8) & 0xFF;
2494
2495 base_hz = base_ratio * bclk * 1000000;
2496 has_base_hz = 1;
2497 return 1;
2498}
1773dump_knl_turbo_ratio_limits(void)
1774{
1775 const unsigned int buckets_no = 7;
1776
1777 unsigned long long msr;
1778 int delta_cores, delta_ratio;
1779 int i, b_nr;
1780 unsigned int cores[buckets_no];

--- 758 unchanged lines hidden (view full) ---

2539
2540 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2541 base_ratio = (msr >> 8) & 0xFF;
2542
2543 base_hz = base_ratio * bclk * 1000000;
2544 has_base_hz = 1;
2545 return 1;
2546}
2547/*
2548 * SLV client has supporet for unique MSRs:
2549 *
2550 * MSR_CC6_DEMOTION_POLICY_CONFIG
2551 * MSR_MC6_DEMOTION_POLICY_CONFIG
2552 */
2553
2554int has_slv_msrs(unsigned int family, unsigned int model)
2555{
2556 if (!genuine_intel)
2557 return 0;
2558
2559 switch (model) {
2560 case INTEL_FAM6_ATOM_SILVERMONT1:
2561 case INTEL_FAM6_ATOM_MERRIFIELD:
2562 case INTEL_FAM6_ATOM_MOOREFIELD:
2563 return 1;
2564 }
2565 return 0;
2566}
2567
2499int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2500{
2568int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2569{
2570 if (has_slv_msrs(family, model))
2571 return 0;
2572
2501 switch (model) {
2502 /* Nehalem compatible, but do not include turbo-ratio limit support */
2503 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2504 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2505 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
2506 case INTEL_FAM6_XEON_PHI_KNM:
2507 return 0;
2508 default:
2509 return 1;
2510 }
2511}
2573 switch (model) {
2574 /* Nehalem compatible, but do not include turbo-ratio limit support */
2575 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2576 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2577 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
2578 case INTEL_FAM6_XEON_PHI_KNM:
2579 return 0;
2580 default:
2581 return 1;
2582 }
2583}
2584int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
2585{
2586 if (has_slv_msrs(family, model))
2587 return 1;
2588
2589 return 0;
2590}
2512int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2513{
2514 if (!genuine_intel)
2515 return 0;
2516
2517 if (family != 6)
2518 return 0;
2519

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2601 dump_hsw_turbo_ratio_limits();
2602
2603 if (has_ivt_turbo_ratio_limit(family, model))
2604 dump_ivt_turbo_ratio_limits();
2605
2606 if (has_nhm_turbo_ratio_limit(family, model))
2607 dump_nhm_turbo_ratio_limits();
2608
2591int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2592{
2593 if (!genuine_intel)
2594 return 0;
2595
2596 if (family != 6)
2597 return 0;
2598

--- 81 unchanged lines hidden (view full) ---

2680 dump_hsw_turbo_ratio_limits();
2681
2682 if (has_ivt_turbo_ratio_limit(family, model))
2683 dump_ivt_turbo_ratio_limits();
2684
2685 if (has_nhm_turbo_ratio_limit(family, model))
2686 dump_nhm_turbo_ratio_limits();
2687
2688 if (has_atom_turbo_ratio_limit(family, model))
2689 dump_atom_turbo_ratio_limits();
2690
2609 if (has_knl_turbo_ratio_limit(family, model))
2610 dump_knl_turbo_ratio_limits();
2611
2612 if (has_config_tdp(family, model))
2613 dump_config_tdp();
2614
2615 dump_nhm_cst_cfg();
2616}

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3282 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3283 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3284 return 1;
3285 }
3286 return 0;
3287}
3288
3289/*
2691 if (has_knl_turbo_ratio_limit(family, model))
2692 dump_knl_turbo_ratio_limits();
2693
2694 if (has_config_tdp(family, model))
2695 dump_config_tdp();
2696
2697 dump_nhm_cst_cfg();
2698}

--- 665 unchanged lines hidden (view full) ---

3364 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3365 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3366 return 1;
3367 }
3368 return 0;
3369}
3370
3371/*
3290 * SLV client has supporet for unique MSRs:
3291 *
3292 * MSR_CC6_DEMOTION_POLICY_CONFIG
3293 * MSR_MC6_DEMOTION_POLICY_CONFIG
3294 */
3295
3296int has_slv_msrs(unsigned int family, unsigned int model)
3297{
3298 if (!genuine_intel)
3299 return 0;
3300
3301 switch (model) {
3302 case INTEL_FAM6_ATOM_SILVERMONT1:
3303 case INTEL_FAM6_ATOM_MERRIFIELD:
3304 case INTEL_FAM6_ATOM_MOOREFIELD:
3305 return 1;
3306 }
3307 return 0;
3308}
3309
3310/*
3311 * HSW adds support for additional MSRs:
3312 *
3313 * MSR_PKG_C8_RESIDENCY 0x00000630
3314 * MSR_PKG_C9_RESIDENCY 0x00000631
3315 * MSR_PKG_C10_RESIDENCY 0x00000632
3316 *
3317 * MSR_PKGC8_IRTL 0x00000633
3318 * MSR_PKGC9_IRTL 0x00000634

--- 1136 unchanged lines hidden --- 		3372 * HSW adds support for additional MSRs:
3373 *
3374 * MSR_PKG_C8_RESIDENCY 0x00000630
3375 * MSR_PKG_C9_RESIDENCY 0x00000631
3376 * MSR_PKG_C10_RESIDENCY 0x00000632
3377 *
3378 * MSR_PKGC8_IRTL 0x00000633
3379 * MSR_PKGC9_IRTL 0x00000634

--- 1136 unchanged lines hidden ---