turbostat.c (cf4cbe5314884c3123fe4ca137e9d750b6e2b8c9) turbostat.c (71616c8e936a6dd541f0627d7bf4ff09971d8ccb)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 3249 unchanged lines hidden (view full) ---

3258 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3259 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3260 return 1;
3261 }
3262 return 0;
3263}
3264
3265/*
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 3249 unchanged lines hidden (view full) ---

3258 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3259 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3260 return 1;
3261 }
3262 return 0;
3263}
3264
3265/*
3266 * SLV client has supporet for unique MSRs:
3267 *
3268 * MSR_CC6_DEMOTION_POLICY_CONFIG
3269 * MSR_MC6_DEMOTION_POLICY_CONFIG
3270 */
3271
3272int has_slv_msrs(unsigned int family, unsigned int model)
3273{
3274 if (!genuine_intel)
3275 return 0;
3276
3277 switch (model) {
3278 case INTEL_FAM6_ATOM_SILVERMONT1:
3279 case INTEL_FAM6_ATOM_MERRIFIELD:
3280 case INTEL_FAM6_ATOM_MOOREFIELD:
3281 return 1;
3282 }
3283 return 0;
3284}
3285
3286/*
3266 * HSW adds support for additional MSRs:
3267 *
3268 * MSR_PKG_C8_RESIDENCY 0x00000630
3269 * MSR_PKG_C9_RESIDENCY 0x00000631
3270 * MSR_PKG_C10_RESIDENCY 0x00000632
3271 *
3272 * MSR_PKGC8_IRTL 0x00000633
3273 * MSR_PKGC9_IRTL 0x00000634

--- 217 unchanged lines hidden (view full) ---

3491
3492 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3493 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3494 base_cpu, msr,
3495 msr & (1 << 0) ? "DIS" : "EN",
3496 msr & (1 << 1) ? "EN" : "DIS",
3497 msr & (1 << 8) ? "EN" : "DIS");
3498}
3287 * HSW adds support for additional MSRs:
3288 *
3289 * MSR_PKG_C8_RESIDENCY 0x00000630
3290 * MSR_PKG_C9_RESIDENCY 0x00000631
3291 * MSR_PKG_C10_RESIDENCY 0x00000632
3292 *
3293 * MSR_PKGC8_IRTL 0x00000633
3294 * MSR_PKGC9_IRTL 0x00000634

--- 217 unchanged lines hidden (view full) ---

3512
3513 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3514 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3515 base_cpu, msr,
3516 msr & (1 << 0) ? "DIS" : "EN",
3517 msr & (1 << 1) ? "EN" : "DIS",
3518 msr & (1 << 8) ? "EN" : "DIS");
3519}
3520/*
3521 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3522 *
3523 * This MSRs are present on Silvermont processors,
3524 * Intel Atom processor E3000 series (Baytrail), and friends.
3525 */
3526void decode_c6_demotion_policy_msr(void)
3527{
3528 unsigned long long msr;
3499
3529
3530 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
3531 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3532 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3533
3534 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
3535 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3536 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3537}
3538
3500void process_cpuid()
3501{
3502 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
3503 unsigned int fms, family, model, stepping;
3504
3505 eax = ebx = ecx = edx = 0;
3506
3507 __cpuid(0, max_level, ebx, ecx, edx);

--- 187 unchanged lines hidden (view full) ---

3695 do_irtl_hsw = has_hsw_msrs(family, model);
3696 do_skl_residency = has_skl_msrs(family, model);
3697 do_slm_cstates = is_slm(family, model);
3698 do_knl_cstates = is_knl(family, model);
3699
3700 if (debug)
3701 decode_misc_pwr_mgmt_msr();
3702
3539void process_cpuid()
3540{
3541 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
3542 unsigned int fms, family, model, stepping;
3543
3544 eax = ebx = ecx = edx = 0;
3545
3546 __cpuid(0, max_level, ebx, ecx, edx);

--- 187 unchanged lines hidden (view full) ---

3734 do_irtl_hsw = has_hsw_msrs(family, model);
3735 do_skl_residency = has_skl_msrs(family, model);
3736 do_slm_cstates = is_slm(family, model);
3737 do_knl_cstates = is_knl(family, model);
3738
3739 if (debug)
3740 decode_misc_pwr_mgmt_msr();
3741
3742 if (debug && has_slv_msrs(family, model))
3743 decode_c6_demotion_policy_msr();
3744
3703 rapl_probe(family, model);
3704 perf_limit_reasons_probe(family, model);
3705
3706 if (debug)
3707 dump_cstate_pstate_config_info(family, model);
3708
3709 if (has_skl_msrs(family, model))
3710 calculate_tsc_tweak();

--- 671 unchanged lines hidden --- 		3745 rapl_probe(family, model);
3746 perf_limit_reasons_probe(family, model);
3747
3748 if (debug)
3749 dump_cstate_pstate_config_info(family, model);
3750
3751 if (has_skl_msrs(family, model))
3752 calculate_tsc_tweak();

--- 671 unchanged lines hidden ---