turbostat.c (be23c9d20b341a58ad7107f9e9aa5735cea3da13) turbostat.c (ec0adc539b8bf59b7c00db0748671f6594b77843)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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1168}
1169
1170static void
1171dump_nhm_platform_info(void)
1172{
1173 unsigned long long msr;
1174 unsigned int ratio;
1175
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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1168}
1169
1170static void
1171dump_nhm_platform_info(void)
1172{
1173 unsigned long long msr;
1174 unsigned int ratio;
1175
1176 get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
1176 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1177
1177
1178 fprintf(stderr, "cpu%d: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1178 fprintf(stderr, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1179
1180 ratio = (msr >> 40) & 0xFF;
1181 fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency frequency\n",
1182 ratio, bclk, ratio * bclk);
1183
1184 ratio = (msr >> 8) & 0xFF;
1185 fprintf(stderr, "%d * %.0f = %.0f MHz base frequency\n",
1186 ratio, bclk, ratio * bclk);

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1802 exit(-6);
1803}
1804
1805/*
1806 * NHM adds support for additional MSRs:
1807 *
1808 * MSR_SMI_COUNT 0x00000034
1809 *
1179
1180 ratio = (msr >> 40) & 0xFF;
1181 fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency frequency\n",
1182 ratio, bclk, ratio * bclk);
1183
1184 ratio = (msr >> 8) & 0xFF;
1185 fprintf(stderr, "%d * %.0f = %.0f MHz base frequency\n",
1186 ratio, bclk, ratio * bclk);

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1802 exit(-6);
1803}
1804
1805/*
1806 * NHM adds support for additional MSRs:
1807 *
1808 * MSR_SMI_COUNT 0x00000034
1809 *
1810 * MSR_NHM_PLATFORM_INFO 0x000000ce
1810 * MSR_PLATFORM_INFO 0x000000ce
1811 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
1812 *
1813 * MSR_PKG_C3_RESIDENCY 0x000003f8
1814 * MSR_PKG_C6_RESIDENCY 0x000003f9
1815 * MSR_CORE_C3_RESIDENCY 0x000003fc
1816 * MSR_CORE_C6_RESIDENCY 0x000003fd
1817 *
1818 * Side effect:

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1871 pkg_cstate_limits = phi_pkg_cstate_limits;
1872 break;
1873 default:
1874 return 0;
1875 }
1876 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1877 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
1878
1811 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
1812 *
1813 * MSR_PKG_C3_RESIDENCY 0x000003f8
1814 * MSR_PKG_C6_RESIDENCY 0x000003f9
1815 * MSR_CORE_C3_RESIDENCY 0x000003fc
1816 * MSR_CORE_C6_RESIDENCY 0x000003fd
1817 *
1818 * Side effect:

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1871 pkg_cstate_limits = phi_pkg_cstate_limits;
1872 break;
1873 default:
1874 return 0;
1875 }
1876 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1877 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
1878
1879 get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
1879 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1880 base_ratio = (msr >> 8) & 0xFF;
1881
1882 base_hz = base_ratio * bclk * 1000000;
1883 has_base_hz = 1;
1884 return 1;
1885}
1886int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
1887{

--- 1342 unchanged lines hidden --- 		1880 base_ratio = (msr >> 8) & 0xFF;
1881
1882 base_hz = base_ratio * bclk * 1000000;
1883 has_base_hz = 1;
1884 return 1;
1885}
1886int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
1887{

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