turbostat.c (b2c95d90a799c9885661d431034b7ca733cc2660) turbostat.c (e6f9bb3cc63346e457405ef30209b3d2e18c5992)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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75unsigned int do_rapl;
76unsigned int do_dts;
77unsigned int do_ptm;
78unsigned int tcc_activation_temp;
79unsigned int tcc_activation_temp_override;
80double rapl_power_units, rapl_energy_units, rapl_time_units;
81double rapl_joule_counter_range;
82
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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75unsigned int do_rapl;
76unsigned int do_dts;
77unsigned int do_ptm;
78unsigned int tcc_activation_temp;
79unsigned int tcc_activation_temp_override;
80double rapl_power_units, rapl_energy_units, rapl_time_units;
81double rapl_joule_counter_range;
82
83#define RAPL_PKG (1 << 0)
84#define RAPL_CORES (1 << 1)
85#define RAPL_GFX (1 << 2)
86#define RAPL_DRAM (1 << 3)
87#define RAPL_PKG_PERF_STATUS (1 << 4)
88#define RAPL_DRAM_PERF_STATUS (1 << 5)
89#define RAPL_PKG_POWER_INFO (1 << 6)
90#define RAPL_CORE_POLICY (1 << 7)
83#define RAPL_PKG (1 << 0)
84 /* 0x610 MSR_PKG_POWER_LIMIT */
85 /* 0x611 MSR_PKG_ENERGY_STATUS */
86#define RAPL_PKG_PERF_STATUS (1 << 1)
87 /* 0x613 MSR_PKG_PERF_STATUS */
88#define RAPL_PKG_POWER_INFO (1 << 2)
89 /* 0x614 MSR_PKG_POWER_INFO */
90
91#define RAPL_DRAM (1 << 3)
92 /* 0x618 MSR_DRAM_POWER_LIMIT */
93 /* 0x619 MSR_DRAM_ENERGY_STATUS */
94 /* 0x61c MSR_DRAM_POWER_INFO */
95#define RAPL_DRAM_PERF_STATUS (1 << 4)
96 /* 0x61b MSR_DRAM_PERF_STATUS */
97
98#define RAPL_CORES (1 << 5)
99 /* 0x638 MSR_PP0_POWER_LIMIT */
100 /* 0x639 MSR_PP0_ENERGY_STATUS */
101#define RAPL_CORE_POLICY (1 << 6)
102 /* 0x63a MSR_PP0_POLICY */
103
104
105#define RAPL_GFX (1 << 7)
106 /* 0x640 MSR_PP1_POWER_LIMIT */
107 /* 0x641 MSR_PP1_ENERGY_STATUS */
108 /* 0x642 MSR_PP1_POLICY */
91#define TJMAX_DEFAULT 100
92
93#define MAX(a, b) ((a) > (b) ? (a) : (b))
94
95int aperf_mperf_unstable;
96int backwards_count;
97char *progname;
98

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1444 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
1445 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
1446 case 0x2C: /* Westmere EP - Gulftown */
1447 case 0x2A: /* SNB */
1448 case 0x2D: /* SNB Xeon */
1449 case 0x3A: /* IVB */
1450 case 0x3E: /* IVB Xeon */
1451 case 0x3C: /* HSW */
109#define TJMAX_DEFAULT 100
110
111#define MAX(a, b) ((a) > (b) ? (a) : (b))
112
113int aperf_mperf_unstable;
114int backwards_count;
115char *progname;
116

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1462 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
1463 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
1464 case 0x2C: /* Westmere EP - Gulftown */
1465 case 0x2A: /* SNB */
1466 case 0x2D: /* SNB Xeon */
1467 case 0x3A: /* IVB */
1468 case 0x3E: /* IVB Xeon */
1469 case 0x3C: /* HSW */
1452 case 0x3F: /* HSW */
1470 case 0x3F: /* HSX */
1453 case 0x45: /* HSW */
1454 case 0x46: /* HSW */
1455 case 0x37: /* BYT */
1456 case 0x4D: /* AVN */
1457 return 1;
1458 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1459 case 0x2F: /* Westmere-EX Xeon - Eagleton */
1460 default:

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1560
1561 if (family != 6)
1562 return;
1563
1564 switch (model) {
1565 case 0x2A:
1566 case 0x3A:
1567 case 0x3C: /* HSW */
1471 case 0x45: /* HSW */
1472 case 0x46: /* HSW */
1473 case 0x37: /* BYT */
1474 case 0x4D: /* AVN */
1475 return 1;
1476 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1477 case 0x2F: /* Westmere-EX Xeon - Eagleton */
1478 default:

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1578
1579 if (family != 6)
1580 return;
1581
1582 switch (model) {
1583 case 0x2A:
1584 case 0x3A:
1585 case 0x3C: /* HSW */
1568 case 0x3F: /* HSW */
1569 case 0x45: /* HSW */
1570 case 0x46: /* HSW */
1571 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
1572 break;
1586 case 0x45: /* HSW */
1587 case 0x46: /* HSW */
1588 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
1589 break;
1590 case 0x3F: /* HSX */
1591 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
1592 break;
1573 case 0x2D:
1574 case 0x3E:
1575 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
1576 break;
1577 case 0x37: /* BYT */
1578 case 0x4D: /* AVN */
1579 do_rapl = RAPL_PKG | RAPL_CORES ;
1580 break;

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2361 }
2362}
2363
2364int main(int argc, char **argv)
2365{
2366 cmdline(argc, argv);
2367
2368 if (verbose)
1593 case 0x2D:
1594 case 0x3E:
1595 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
1596 break;
1597 case 0x37: /* BYT */
1598 case 0x4D: /* AVN */
1599 do_rapl = RAPL_PKG | RAPL_CORES ;
1600 break;

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2381 }
2382}
2383
2384int main(int argc, char **argv)
2385{
2386 cmdline(argc, argv);
2387
2388 if (verbose)
2369 fprintf(stderr, "turbostat v3.5 April 26, 2013"
2389 fprintf(stderr, "turbostat v3.6 Dec 2, 2013"
2370 " - Len Brown <lenb@kernel.org>\n");
2371
2372 turbostat_init();
2373
2374 /*
2375 * if any params left, it must be a command to fork
2376 */
2377 if (argc - optind)
2378 return fork_it(argv + optind);
2379 else
2380 turbostat_loop();
2381
2382 return 0;
2383}
2390 " - Len Brown <lenb@kernel.org>\n");
2391
2392 turbostat_init();
2393
2394 /*
2395 * if any params left, it must be a command to fork
2396 */
2397 if (argc - optind)
2398 return fork_it(argv + optind);
2399 else
2400 turbostat_loop();
2401
2402 return 0;
2403}