turbostat.c (48f87dd146a480c723774962eca675873a8aa1da) turbostat.c (21ed5574d1622118b49b0c6342acc8d27d0799be)
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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70unsigned int extra_msr_offset32;
71unsigned int extra_msr_offset64;
72unsigned int extra_delta_offset32;
73unsigned int extra_delta_offset64;
74unsigned int aperf_mperf_multiplier = 1;
75int do_smi;
76double bclk;
77double base_hz;
1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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70unsigned int extra_msr_offset32;
71unsigned int extra_msr_offset64;
72unsigned int extra_delta_offset32;
73unsigned int extra_delta_offset64;
74unsigned int aperf_mperf_multiplier = 1;
75int do_smi;
76double bclk;
77double base_hz;
78unsigned int has_base_hz;
78double tsc_tweak = 1.0;
79unsigned int show_pkg;
80unsigned int show_core;
81unsigned int show_cpu;
82unsigned int show_pkg_only;
83unsigned int show_core_only;
84char *output_buffer, *outp;
85unsigned int do_rapl;

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91double rapl_dram_energy_units, rapl_energy_units;
92double rapl_joule_counter_range;
93unsigned int do_core_perf_limit_reasons;
94unsigned int do_gfx_perf_limit_reasons;
95unsigned int do_ring_perf_limit_reasons;
96unsigned int crystal_hz;
97unsigned long long tsc_hz;
98int base_cpu;
79double tsc_tweak = 1.0;
80unsigned int show_pkg;
81unsigned int show_core;
82unsigned int show_cpu;
83unsigned int show_pkg_only;
84unsigned int show_core_only;
85char *output_buffer, *outp;
86unsigned int do_rapl;

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92double rapl_dram_energy_units, rapl_energy_units;
93double rapl_joule_counter_range;
94unsigned int do_core_perf_limit_reasons;
95unsigned int do_gfx_perf_limit_reasons;
96unsigned int do_ring_perf_limit_reasons;
97unsigned int crystal_hz;
98unsigned long long tsc_hz;
99int base_cpu;
100double discover_bclk(unsigned int family, unsigned int model);
99
100#define RAPL_PKG (1 << 0)
101 /* 0x610 MSR_PKG_POWER_LIMIT */
102 /* 0x611 MSR_PKG_ENERGY_STATUS */
103#define RAPL_PKG_PERF_STATUS (1 << 1)
104 /* 0x613 MSR_PKG_PERF_STATUS */
105#define RAPL_PKG_POWER_INFO (1 << 2)
106 /* 0x614 MSR_PKG_POWER_INFO */

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506 if (has_aperf) {
507 if (!skip_c0)
508 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
509 else
510 outp += sprintf(outp, "********");
511 }
512
513 /* Bzy_MHz */
101
102#define RAPL_PKG (1 << 0)
103 /* 0x610 MSR_PKG_POWER_LIMIT */
104 /* 0x611 MSR_PKG_ENERGY_STATUS */
105#define RAPL_PKG_PERF_STATUS (1 << 1)
106 /* 0x613 MSR_PKG_PERF_STATUS */
107#define RAPL_PKG_POWER_INFO (1 << 2)
108 /* 0x614 MSR_PKG_POWER_INFO */

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508 if (has_aperf) {
509 if (!skip_c0)
510 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
511 else
512 outp += sprintf(outp, "********");
513 }
514
515 /* Bzy_MHz */
514 if (has_aperf)
515 outp += sprintf(outp, "%8.0f",
516 1.0 * t->tsc * tsc_tweak / units * t->aperf / t->mperf / interval_float);
516 if (has_aperf) {
517 if (has_base_hz)
518 outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf);
519 else
520 outp += sprintf(outp, "%8.0f",
521 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
522 }
517
518 /* TSC_MHz */
519 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
520
521 /* delta */
522 if (extra_delta_offset32)
523 outp += sprintf(outp, " %11llu", t->extra_delta32);
524

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1153int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1154int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1155int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1156
1157
1158static void
1159calculate_tsc_tweak()
1160{
523
524 /* TSC_MHz */
525 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
526
527 /* delta */
528 if (extra_delta_offset32)
529 outp += sprintf(outp, " %11llu", t->extra_delta32);
530

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1159int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1160int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1161int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1162
1163
1164static void
1165calculate_tsc_tweak()
1166{
1161 unsigned long long msr;
1162 unsigned int base_ratio;
1163
1164 get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
1165 base_ratio = (msr >> 8) & 0xFF;
1166 base_hz = base_ratio * bclk * 1000000;
1167 tsc_tweak = base_hz / tsc_hz;
1168}
1169
1170static void
1171dump_nhm_platform_info(void)
1172{
1173 unsigned long long msr;
1174 unsigned int ratio;

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1816 * MSR_CORE_C6_RESIDENCY 0x000003fd
1817 *
1818 * Side effect:
1819 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
1820 */
1821int probe_nhm_msrs(unsigned int family, unsigned int model)
1822{
1823 unsigned long long msr;
1167 tsc_tweak = base_hz / tsc_hz;
1168}
1169
1170static void
1171dump_nhm_platform_info(void)
1172{
1173 unsigned long long msr;
1174 unsigned int ratio;

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1816 * MSR_CORE_C6_RESIDENCY 0x000003fd
1817 *
1818 * Side effect:
1819 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
1820 */
1821int probe_nhm_msrs(unsigned int family, unsigned int model)
1822{
1823 unsigned long long msr;
1824 unsigned int base_ratio;
1824 int *pkg_cstate_limits;
1825
1826 if (!genuine_intel)
1827 return 0;
1828
1829 if (family != 6)
1830 return 0;
1831
1825 int *pkg_cstate_limits;
1826
1827 if (!genuine_intel)
1828 return 0;
1829
1830 if (family != 6)
1831 return 0;
1832
1833 bclk = discover_bclk(family, model);
1834
1832 switch (model) {
1833 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
1834 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
1835 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
1836 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
1837 case 0x2C: /* Westmere EP - Gulftown */
1838 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1839 case 0x2F: /* Westmere-EX Xeon - Eagleton */

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1866 break;
1867 case 0x57: /* PHI */
1868 pkg_cstate_limits = phi_pkg_cstate_limits;
1869 break;
1870 default:
1871 return 0;
1872 }
1873 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1835 switch (model) {
1836 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
1837 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
1838 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
1839 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
1840 case 0x2C: /* Westmere EP - Gulftown */
1841 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1842 case 0x2F: /* Westmere-EX Xeon - Eagleton */

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1869 break;
1870 case 0x57: /* PHI */
1871 pkg_cstate_limits = phi_pkg_cstate_limits;
1872 break;
1873 default:
1874 return 0;
1875 }
1876 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1874
1875 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
1876
1877 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
1878
1879 get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
1880 base_ratio = (msr >> 8) & 0xFF;
1881
1882 base_hz = base_ratio * bclk * 1000000;
1883 has_base_hz = 1;
1877 return 1;
1878}
1879int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
1880{
1881 switch (model) {
1882 /* Nehalem compatible, but do not include turbo-ratio limit support */
1883 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1884 case 0x2F: /* Westmere-EX Xeon - Eagleton */

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2775 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
2776 do_pc3 = (pkg_cstate_limit >= PCL__3);
2777 do_pc6 = (pkg_cstate_limit >= PCL__6);
2778 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
2779 do_c8_c9_c10 = has_hsw_msrs(family, model);
2780 do_skl_residency = has_skl_msrs(family, model);
2781 do_slm_cstates = is_slm(family, model);
2782 do_knl_cstates = is_knl(family, model);
1884 return 1;
1885}
1886int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
1887{
1888 switch (model) {
1889 /* Nehalem compatible, but do not include turbo-ratio limit support */
1890 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1891 case 0x2F: /* Westmere-EX Xeon - Eagleton */

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2782 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
2783 do_pc3 = (pkg_cstate_limit >= PCL__3);
2784 do_pc6 = (pkg_cstate_limit >= PCL__6);
2785 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
2786 do_c8_c9_c10 = has_hsw_msrs(family, model);
2787 do_skl_residency = has_skl_msrs(family, model);
2788 do_slm_cstates = is_slm(family, model);
2789 do_knl_cstates = is_knl(family, model);
2783 bclk = discover_bclk(family, model);
2784
2785 rapl_probe(family, model);
2786 perf_limit_reasons_probe(family, model);
2787
2788 if (debug)
2789 dump_cstate_pstate_config_info();
2790
2791 if (has_skl_msrs(family, model))

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2791 rapl_probe(family, model);
2792 perf_limit_reasons_probe(family, model);
2793
2794 if (debug)
2795 dump_cstate_pstate_config_info();
2796
2797 if (has_skl_msrs(family, model))

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